From the course: Learning Verilog for FPGA Development

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Clock generation

Clock generation - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Clock generation

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- [Instructor] Another type of stimulus variable you'll need in sequential systems is a clock signal. This is usually a square wave that changes between zero and one periodically. This requires another block in a test bench module, and it's extremely easy to implement. First, you declare a register for this signal. It's almost always named lowercase C-L-K. Then, in another part of the code, you must initialize this register to some value. Here I'm using zero. Notice that I'm using a one-line Initial block. Then finally, you need to assign to this clock variable, the complement of its current value. This is done with the NOT operator. Notice that this is a one-line Always block with a delay of five time units. This means that this signal will oscillate at a period of 10 time units.

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