From the course: Learning Verilog for FPGA Development

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Challenge: Make a clock divider

Challenge: Make a clock divider - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Challenge: Make a clock divider

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(quirky music) - Once more it's time to test your knowledge with a nice challenge. Now you must write a Verilog module for a clock frequency divider. This would useful in a system where you have a high frequency clock. Say 100 megahertz. And you need a 240 hertz signal. You can do this by receiving the fast clock signal. Count cycles. And output a slower signal based on this count. This is the declaration for the clock divider. The input and output signals are called clock in and clock out respectively. There's a reset input which is usually active low. So you may initialize the internal registers when it's line goes low. And finally, there's a ratio input which is a 32 bit number. This input will be used to let the divider know the ratio at which you want to reduce the frequency. For example, if you have an input frequency of 100 megahertz and you want to output a one kilohertz signal. Then the ratio should be…

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