From the course: Learning Verilog for FPGA Development
Join today to access over 23,200 courses taught by industry experts.
A functional demo of the clock divider - FPGA Tutorial
From the course: Learning Verilog for FPGA Development
A functional demo of the clock divider
- [Instructor] So here we have the sequential application running on the Digilent Basys 3 board. Now, there are two things I want you to notice. First, the display is behaving exactly as we intended, alternating between zero and one at a frequency of exactly one hertz. That's zero for the first half of a second, and one for the remaining half. The second thing I want you to notice is the rightmost LED, which is supposed to be blinking at 100 megahertz. Now, since this is a very, very high frequency, all we get to see is a dim light. Now the brightness of this LED is supposed to look dimmer than the other green LED at the top right of the board. That's because the clock signal probably has a duty cycle of about 50%.
Practice while you learn with exercise files
Download the files the instructor uses to teach the course. Follow along and learn by watching, listening and practicing.
Download courses and learn on the go
Watch courses on your mobile device without an internet connection. Download courses using your iOS or Android LinkedIn Learning app.