From the course: Learning FPGA Development
Join today to access over 23,200 courses taught by industry experts.
Simulation - FPGA Tutorial
From the course: Learning FPGA Development
Simulation
- [Instructor] Let's take a look at some of the basic elements of Verilog Simulation. Simulations are specified by test bench modules. And these modules must instantiate whatever module you want to test out. Your test bench is supposed to provide input signals to that module under test. And the simulation consists on running the sequence of events you specify. The behavior of your module under test, will determine the results of this simulation. Now, here we have a few pointers on the syntax used in test bench modules in Verilog. A test bench is not required to specify ports. Because you're usually interested in running a sequence. Providing your own values to the module under test. You must separate events in time somehow. For this, you can instruct the simulator to wait for some time with the pound symbol. For example, pound 10, means wait for 10 units of time. These ten units could be nanoseconds, microseconds, or any other duration you want. The body of a test bench is usually a…
Practice while you learn with exercise files
Download the files the instructor uses to teach the course. Follow along and learn by watching, listening and practicing.
Download courses and learn on the go
Watch courses on your mobile device without an internet connection. Download courses using your iOS or Android LinkedIn Learning app.