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Sequential logic simulation example

Sequential logic simulation example - FPGA Tutorial

From the course: Learning FPGA Development

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Sequential logic simulation example

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- [Instructor] Now let's take a look at a sequential simulation. We will do this in Vivado, and I will start by showing you the lowest level module, that is, the module under Test. This module is a counter, a four-bit up-down counter. It has a CLK input, a UD input which is a line that determines if the counter will count up or down. It has an output that's a register of four bits which is the Count, and lastly, it has a Clear input to reset the Count to zero. If you pay attention to line 12, you'll see that there's an always block that works whenever the Clear line changes, and if the Clear line is zero, then the Count goes back to zero. In line 16, we have another always block that works on the positive edge of the CLK line, and its code is a case statement that pays attention to the concatenation of the UD and the Clear lines so that when the UD line is zero, the counter will count down, and when the UD line is one, the counter will count up. That's it for the counter. So now…

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