Vitali Tupikov

In this podcast Brad Griffin discusses signal and power integrity decision making. Discover how you can eliminate the back and forth between PCB designers and electrical engineers using new SI/PI methodologies. Listen to Episode 4 of I-Connect007's "On the Line With... Cadence" series now! https://bit.ly/3JRFlud #PCBDesign #Cadence

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Easily incorporate Cadence tools into your curriculum with our education kits. Use the Analog Simulation and Layout kit to teach the fundamentals of analog simulation and layout using Cadence Virtuoso technology, including how to enter a schematic, run basic simulations, create a simple layout, and more! Download today ⤵️ https://ow.ly/708k50S7L2b #analogsimulation #virtuoso

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Interested in laminates at millimeter wave frequencies? Learn more in the May issue! "Theory vs. Reality: Using Printed Circuit Board Technology for Grounded Coplanar Waveguide at Millimeter-Wave Frequencies" by John Coonrod. This paper presents a rigorous theoretical design approach for millimeter-wave grounded coplanar waveguides fabricated from printed circuit boards and compares realized performance to theory. https://lnkd.in/eSAcsVhN #MicrowaveTechnology #Innovation #MicrowaveMagazine #AprilIssue #MicrowaveEngineering #Laminate

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blind vias are more complex and expensive to manufacture compared to through-hole vias, due to the additional steps required in the drilling and plating processes. Here's a brief overview of the different types of vias and their functions: Through-hole vias: These pass through the entire PCB, connecting all layers. They are the simplest and most common type of via. Blind vias: These connect an outer layer to one or more inner layers but do not go through the entire board. They start on an outer layer and end on an inner layer, which helps save space and reduce the number of holes drilled through the board. Buried vias: These are located entirely within the inner layers of the PCB and do not extend to the outer layers. They connect two or more inner layers without being visible from the outside. #WearableTech #PrototypePCB #PCBManufacturing #FlexiblePCBs #ConsumerElectronics #PCBDesign #HardwareDesign #CircuitDesign #AerospaceTech

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6 Steps of Semiconductor Testing (for non-engineers): 🔍 Wafer Probing: Imagine a large circular slice of semiconductor material loaded with countless tiny electronic chips. Wafer probing is like giving each chip a quick check-up before they're separated and packaged. It ensures they're working correctly right from the start, like a preliminary health screening for electronics! 💡 Fine Pitch & Micro Bumped Wafers: To pack more circuits into smaller spaces, engineers use innovative techniques like fine pitch and micro bumped wafers. Think of it as fitting more passengers onto a bus without overcrowding – it's about maximizing efficiency and space utilization on the semiconductor wafer. 🔌 DC to Full RF Probing: Now, let's talk about the tools used in wafer probing – probe cards. These nifty gadgets are designed to handle various electrical signals, from the steady flow of Direct Current (DC) to the speedy transmissions of Radio Frequency (RF). It's like having a versatile tool belt for testing electronic circuits of all kinds! 🚀 High Multisites Testing: Testing one chip at a time is efficient, but testing multiple chips simultaneously is even better! High multisites testing allows engineers to check several chips on the same wafer at once, speeding up the process like scanning multiple items at a grocery store checkout. Efficiency at its finest! 📊 Wafer Sorting Interface: Once the chips are probed and tested, it's time to sort them based on their performance and quality. This process is akin to grading exam papers – chips that meet the standards get a pass, while those that fall short are flagged for further inspection or adjustments. It's all about ensuring only the best chips make it to the final product! 🔬 Final Testing: Before the chips are packaged and shipped off to power our devices, they undergo one last round of rigorous testing. This final check ensures that each chip meets the highest standards of quality and reliability. It's like the grand finale of a fireworks show – a dazzling display of precision and perfection! For opportunities to work on semiconductor test processes, contact us at DELVE Search! #semiconductor #semiconductorjobs #semiconductortest #osat #advancedpackaging

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Tired of tedious DC I-V and C-V testing? 🙄 Testing power semiconductors shouldn't be a frustrating, time-consuming, and error-prone process. This application note offers a solution that will revolutionize your testing process: 📌 Minimize connection changes, simplifying your setup. 📌 Reduce user error, improving accuracy. 📌 Streamline testing, saving you valuable time. Don't let cumbersome testing procedures hold you back. Join the revolution and embrace a smarter approach to semiconductor testing. 💡 Read the App Note here ➡️ https://lnkd.in/d7wjE4cN #Semiconductor #SemiconductorIndustry #TestEngineer

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Some PCB debates never go away, and one of the most prolific PCB design debates is the use of non-functional pads (NFPs). Here’s what you should consider if you are thinking of removing all NFPs from your PCB. https://bit.ly/4e5OaP1 #AllegroX #Cadence

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Signal integrity simulations are crucial when designing high-speed PCBs. But here's the catch: manufacturing processes come with tolerances, impacting impedance targets and might not cover the range of its variance. Using CST SI tools, we've created a test case that illuminates the balance between signal integrity compliance and manufacturing realities. Curious to learn more? Check out the video in our Knowledge Hub in the link below!

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PCB line spacing is critical for both safety and function in high voltage circuitry. San Francisco Circuits has released a new in-depth article on PCB Line Spacing for high voltage applications >> 🔗 https://hubs.la/Q02FSSvM0 In the full article, San Francisco Circuits discusses how proper line spacing can prevent issues like arcing by following established safety standards. Additionally, clearance and creepage distances are crucial to avoid electrical faults in high voltage circuits. 👏 Visit the Unmanned Systems Technology website for further information. #unmanned #technology #electronics #future #safety

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Introducing the latest release! Discover Version 4.5 of the Power IC Model Library for Cadence® PSpice®. At AEi Systems, renowned for our expertise in worst-case circuit analysis, we recognize the criticality of precise circuit simulations. Your simulations' efficacy hinges on the quality of component models. Ensure precise design simulations with our extensive collection of over 1,700 meticulously crafted and correlated models. Benefit from our bench-tested models, accurately curated to compensate for the absence of manufacturer data. Get these now at EMA Design Automation®   Key benefits include: * Hard to find models * Verified and Documented - Model Correlations * SPACE Rad-Hard ISL, RH, UC Models * Regulators, Switchers, LDO, Power Semis and more * Automotive Stimulus and Test Patterns * Analysis in Time and Frequency Domain (AC models) https://lnkd.in/gqhMbCfE

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#ConsumerElectronics #Embedded   Fuel gauging is a critical component of today’s rechargeable embedded devices. In this episode of Chalk Talk, Amelia Dalton and Robin Saltnes of Nordic Semiconductor explore the variety of benefits that Nordic Semiconductor’s nPM1300 PMIC brings to rechargeable embedded devices, the details of the fuel gauge system at the heart of this solution and … Read More → "Ultra-low Power Fuel Gauging for Rechargeable Embedded Devices – Nordic Semiconductor and Mouser" https://lnkd.in/gdhWd2Vx

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With the greater bandwidth requirements of #5G and beyond, die size becomes a challenge as smartphones and other connected devices need to pack in more RF components without increasing surface area. Enter #3DIC technology. UMC's 3D IC solution for RFSOI is the first of its kind in the industry. Utilizing wafer-to-wafer bonding technology to stack dies vertically, this solution reduces area by 45% to free up space for additional modules. It also overcomes the common issue in the industry of RF interference between stacked dies. Find out more: https://lnkd.in/guttvJYv #semiconductor #innovation #wirelesscommunication #advancedpackaging

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Summit Interconnect’s Tailored PCBs for the Automated Test Equipment (ATE) Market in Semiconductor Chips Click here to read more https://ow.ly/ff7K50RiO0b Summit Interconnect #core #competencies #capabilities #updates #insights #pcb #industry #circuit #board #automated #test #equipment #market #semiconductor #chip

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Master the art of RF PCB stackup design and ensure optimal signal integrity for your high-frequency analog circuits https://bit.ly/3zfR04j #PCBdesign #Cadence

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The 9th-gen V-NAND features the latest NAND flash interface, "Toggle 5.1," supporting increased data input/output speeds by 33% to up to 3.2 gigabits-per-second (Gbps).

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LTspice Outperforms the Magnetics PhDs I have just posted an LTspice schematic of a buck converter with a Coilcraft inductor. Included are advanced proximity components (including gap loss) for the winding losses and an advanced core loss model. It's the first time we've published the subcircuits and symbols to do this simulation outside of our RidleyWorks user base. Why is it better than the PhDs? (Remember I am one...) A PhD can solve Dowell's equations for you if their focus is on magnetics. Very few industry people even try - our observation shows about 1%. (Even after getting my PhD, I needed help to make my way through them.) A PhD might be able to symbolically solve for harmonics in a given converter. That's ignoring all second order effects. Not many could form the convolution of these two solutions together. Prof. Hurley tried to do that in his book on magnetics, but left out any parasitics like magnetizing current. LTspice effortlessly calculates the proximity losses in real time, without having to separately extract harmonics. It's done in the time domain. I don't know anyone who has done a good gap loss model that is usable. That's included in this simulation. The model is built from ac resistance measurements in the lab. I really like what we have done for core loss models. You can watch the losses change with the different excitations, frequency, and harmonics. Of course, we use RidleyWorks to set up the values for the LTspice circuits. That will save you a huge amount of work for other magnetics parts. Of course, PhDs, feel free to spend a lot of time rederiving them your own special way. All the files you need to run the simulation have been uploaded on in our Facebook group. . Give them a try - let us know what you think.

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"The adoption of SiC in EV power systems represents a significant advancement in the quest for more efficient and sustainable transportation. SiC offers several advantages over traditional silicon-based solutions, making it an ideal choice for EV power electronics applications." A brilliant article on how SiC is transforming power electronics in the automotive industry Credit: Jack Shaw @ Automotive IQ Follow Cubiq Recruitment for industry news, insights, and vacancy updates #siliconcarbide #SiC #powerelectronics #automotive #automotiveengineering #electricvehicles #evs #cubiqrecruitment

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