Retired from AMD
Fort Collins, Colorado, United States
Contact Info
77 followers
72 connections
About
Leader of the AMD Corporate Wide Technology Funnel, System Technology Co Optimization (STCO) team and future Advanced Foundry Technology Nodes. Research and recommend new disruptive technologies for "More than Moore's Law" future technologies to meet the 5+ year AMD product roadmap.
Owner and driver of key AMD design requirements for the development of advanced process foundry technology nodes for 1nm and beyond. Key contributor and member of many AMD teams including Foundry Technology Strategy team, Long Range Manufacturing Lead engineer for logic library IP architectures with a 5+ year horizon and new CAD tool innovations for advanced technologies with 5+ year timeline.
Primary interface between AMD design architects and process technology and consultant to AMD senior executive staff of future technology nodes and disruptive technologies.
Core Competencies:
Advanced Process Technology R&D
Foundry Technology Assessment
Device Physics
Trigate and Gate All Around Transistor Device
Standard Cell Architectures ( Vertical Gate All Around FET, Lateral Gate All Around FET, CFET)
Advanced Logic Routing Studies and CAD Tool Enhancements/Innovation
Design for Performance
Design for Yield
Technology Test Chip and Qualification Schedules
Yield and Reliability Vehicle Design
Lithography - Immersion and EUV
CMP Modeling
Performance/Power/Cost/Area
Process Wafer Cost Model Development
Yield Modeling
Failure Analysis
Statistical Timing Analysis and Tool Development
On Die Power Droop and Electromigration Tool Development and Simulation
2.1, 2.5 and 3D Packaging Technologies and Die Stacking
Experience
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Currently Retired from the Industry
No Longer Employed
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AMD
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Education
Publications
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2012 VLSI Symposium - Designing in Scaled Technologies: 32nm and Beyond
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FSA Forum Magazine – Vol. 14 Number 1, March 2007 – Industry Reflections Interview on Fabless Model and DFM
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LSI World Wide Technical Conference 2006 - Critical Area Analysis and Mitigation Strategies in Deep Submicron Technologies
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Patents
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Apparatuses and Systems for Offset Cross Field-Effect Transistors
US 20240145565
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Auto Cone Logic Schematic And Waveform Generation Tool
US 6,625,770
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CAD Flow for 15nm/22nm Multiple Fine Grained Wimpy Gate Lengths in SIT Gate Flow
US 8,099,686 b2
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CAD flow for 15nm/22nm multiple fine grained wimpy gate lengths in SIT gate flow
US 8,099,686
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Channel Length Scaling for Footprint Compatible Digital Library Cell Design
US 8,397,184
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Chip level clock tree deskew circuit
US 7,023,252
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Concentric Metal Density Power Routing
US 6,476,497
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Cross FET SRAM Cell Layout
US 11,778,803
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Cross Field Effect Transistor (XFET) Library Architecture Power Routing
US 11,881,393
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Cross Field Effect Transistor Library Cell Architecture Design
US 11,882,673
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Defect analysis using a yield vehicle
US 7,284,213
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Device for Avoiding Timing Violations Resulting from Process Defects in a Backfilled Metal Layer of an Integrated Circuit
US 7,392,496
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Double Spacer Immersion Lithography Triple Patterning Flow and Method
US 10,304,728
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Dual-track Bitline Scheme for 6T SRAM cells
US 11,710,698
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Failure Analysis Vehicle for Yield Enhancement with Self Test at Speed Burnin Capability for Reliability Testing
US 7,420,229
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Failure Analysis Vehicle for Yield and Qualification of 90nm Technologies and Beyond
US 6,781,151
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Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testing Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testing
US 7,129,101
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Floor Plan-based Power Bus Analysis and Design Tool for Integrated Circuits
US 6,675,139
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Floor plan development electromigration and voltage drop analysis tool
US 7,016,794
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Folded cell layout for 6T SRAM cell
US 11,437,316
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Fully shielded capacitor cell structure
US 7,154,734
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Gate All Around Architecture With Local Oxide
US 9704995
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Gate All Around Device Architecture With Hybrid Wafer Bond Technique
US 10068794
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Gate Contact Over Active Region in Cell
US 10,818,762
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Gate Contact Over Active Region in Cell
US 11,424,336
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Inset Power Post and Strap Architecture with Reduced Voltage Droop
US 11,652,050
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Instantaneous Voltage Drop Sensitivity Analysis Tool (IVDSAT)
US 7,818,157
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Interconnect Integrity Verification
US 7,424,690
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Load Sensing, Slew Rate Shaping, Output Signal Pad Cell Driver Circuit And Method
US 6,388,486
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Metahardened Flip Flop Architecture
US 5,999,029
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Metal Density Distribution for Double Pattern Lithography
US 10,283,437
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Metal Zero Contact Via Redundancy on Output Nodes and Inset Power Rail Architecture
US 10,438,937
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Metal Zero Power Ground Stub Route to Reduce Cell Area and Improve Cell Placement at the Chip Level
US 11,120,190
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Metal zero contact via redundancy on output nodes and inset power rail architecture
US 10,651,164
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Metastability Risk Simulation Analysis Tool and Method
US 6,408,265
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Method of Automatically Generating Schematic and Waveform Diagrams for Analysis of Timing Margins and Signal Skews of Relevant Logic Cells using Input Signal
US 6,442,741
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Method of Automatically Generating Schmatic and Waveform Diagrams for Isolating Faults From Multiple Failing Paths in a Circuit Using Input Signal Predicators and TransitionTime
US 6,671,846
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Method of Generating A Redistribution Metal Power Bus Pattern For A Wire Bonded Integrated Circuit
US 6,653,726
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Method of Using of Multiple Single Damascene Steps to Build a Thicker Redistribution Layer
US 6,830,984
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Method of creating photlithographic masks for semiconductor device features with reduced design rule violations
US 8,219,939
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Methods for fabricating FinFET structures having different channel lengths
US 7,687,339
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Methods for fabricating FinFET structures having different channel lengths
US 7,829,466
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Methods for fabricating FinFET structures having different channel lengths
US 7,960,287
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N Cell Height Decoupling Circuit
US 7,829,973
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Oscillating Capacitor Architecture in Polysilicon for Improved Capacitance
US 10,608,076
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Power Grid Architecture and Optimization with EUV Lithography
US 11,347,925
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Power Grid Layout Designs for Integrated Circuits
US 11,189,569
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Process for Forming Fins for a FinFET device
US 8,624,320
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Process, Voltage and Temperature Independent Clock Tree Deskew Circuitry
US 6,340,905
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Process, Voltage and Temperature Independent Clock Tree Deskew Circuitry - Active Drive Method
US 6,433,598
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Process, Voltage and Temperature Independent Clock Tree Deskew Circuitry - Temporary Driver Method
US 6,653,883
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Process, Voltage and Temperature Independent Clock Tree Deskew Circuitry - Temporary Driver Method
US 6,429,714
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Radially Increasing Density, Core Power Bus Architecture for a Copper Process
US 6,346,721
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Radially-Increasing Core Power Bus Grid Architecture
US 6,111,310
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Reliability circuit for applying an AC stress signal or DC measurement to a transistor device
US 7,183,791
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Routing and manufacturing with a minimum area metal structure
US 11934764
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SRAM Bit Cell with Self-aligned Bidirectional Local Interconnects
US 8,076,236
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SRAM bit cell with self-aligned bidirectional local interconnects
US 8,076,236
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Selective local interconnect to gate in a self aligned local interconnect process
US 8,563,425
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Self-aligned Trench Contact and Local Interconnect With Replacement Gate Process
US 8,564,030
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Self-timed reliability and yield vehicle array
US 6,861,864
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Self-timed reliability and yield vehicle with gated data and clock
US 7,308,627
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Semiconductor Chip with Stacked Conductor Line and Air Gaps
US 11,004,791
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Semiconductor device fabrication using multiple expeosure and block mask approach to reduce design rule violations
US 8,304,172
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Sinusoidal Shaped Capacitor Architecture in Oxide
US 10,756,164
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Standard Cell Layout Architectures and Drawing Styles for 5nm and Beyond
US 11,211,330
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Standard Cell and Power Grid Architectures with EUV Lithography
US 10,796,061
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Static Timing Analysis and Performance Diagnostic Display Tool
US 6,851,098
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Static timing and risk analysis tool
US 7,181,713
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Test Vehicle Data Analysis
US 7,370,257
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Trench Silicide and Gate Open with Local Interconnect with Replacement Gate Process
US 8,716,124
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Trench silicide and gate open with local interconnect with replacement gate process
US 9,006,834
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Turning Off Clocks to Flip Flops
US 8,347,123
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Turning Off Clocks to Flip Flops
US 7,631,209
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Vertical Gate All Around Library Architecture
US 10,186,510
Projects
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Long Range Manufacturting Stategic Committee
Active member of the long range strategic committee for process foundry and OSAT engagement for AMD's mid and long range manfacturing roadmap. Help drive key alignment and focuses on strategic long term goals to anticipate and align AMD's future technology and product needs and external suppliers.
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Advanced Technology Council
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Lead the effort to respond to slowing process technology performance and increased cost/compexity to keep AMD products moving forward in a "More than Moore's Law" enviroment. Drive key interactions between CPU and GPU design architects, blending design architecture, advanced technology and disruptive technologies into more competitve AMD future roadmap.
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AMD Corporate Wide Technology Funnel
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Owner and leader of the AMD Corporate Wide Technology Funnel. Have successfully moved several disruptive technologies through the AMD Technology Funnel and into the long terms AMD roadmap. The main focus is to deliver "More than Moore's Law" scaling, cost and performance as advanced process technology slows down goinf forward.
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AMD Executive Reviews, Mentoring and Team Participation
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Prepare and review the status of each foundry through regular Foundry meetings and Quarterly Reviews. Meet with CTO and other senior executive staff at each Foundry and within AMD. Have successfully managed and delivered up to three advanced Foundry nodes simultaneously.
Participate in many design and technology cross functional teams. Mentor less experienced engineers and transfer the technology ownership to them as it moves from R&D to test chip and product tape out readiness…Prepare and review the status of each foundry through regular Foundry meetings and Quarterly Reviews. Meet with CTO and other senior executive staff at each Foundry and within AMD. Have successfully managed and delivered up to three advanced Foundry nodes simultaneously.
Participate in many design and technology cross functional teams. Mentor less experienced engineers and transfer the technology ownership to them as it moves from R&D to test chip and product tape out readiness maturity.
Teams Leadership Roles Include:
Advanced Corporate Wide Technology Funnel
Advanced Technology Council
New Standard Cell Architectures
Quarterly Foundry Reviews
Weekly AMD Internal Design and Technology Interlocks
Regular Foundry Technical Exchange
Yearly Summary of Conferences - IEDM...other
Future Process Roadmap Executive Updates
Team Participation Roles Include:
SEO Strategy Team
FTO Strategy Team
Performance/Power/Cost Tiger Team
Node Owners Best Practices
AMD Test Chip and Shuttle Planning
Design for Manufacturability
Paper Submission Reviews for IEDM, VLSI
Process Technology Competitive Analysis -
AMD Future Foundry Technology R&D
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Collaborate with leading edge Foundries to define and develop early requirements for future process technology offerings that meet AMD's 3-5 year product roadmap. Owner of all aspects of the technology which include cost reduction, scaling, performance, power, reliability, schedule and AMD product or technology component requirements to be enabled for future products. Past delivered technologies have spanned 45nm-7nm.
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Design For Manufacturing Tool Flow and Qualification Lead
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Lead Engineer for the tool qualification and analysis of lithography simulations, chemical mechanical polish simulations and critical area analysis simulations associated with external Foundry Process Technology. Responsible for model to silicon correlation at the cell level and chip level.
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Dynamic Power Droop CAD Tool Develoment and Deployment
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Developed and successfully deployed a power droop sensitivity analysis tool with a graphical layout interface which could model dynamic power mesh droop based on various voltage dependent injected current wave shapes and magnitude by power zone or area on the power mesh. It could output max droop over time or a full dynamic video of the simulation results. The tool was written in Perl5 and Perl Tk.
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Former Si2 and FSA Panel Member for DFM and Models
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Participated and contributed to working groups within FSA and Si2 on design for manufacturability with focus on areas such as lithography and chemical mechanical polish modeling and methodology.
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New Standard Cell Architectures
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Key architect for the design and development new standard cell architectures to improve scaling and routability of advanced process technology nodes to provide hyper scaling and improved cost, power, power droop and reliability. Implemented new architectures to several AMD technology nodes that enabled true AMD hyper scaling. Several hundred million dollar ROI savings expected over technology lifetime. Proposed new architectures for future nodes for improved cell placment utilization, power…
Key architect for the design and development new standard cell architectures to improve scaling and routability of advanced process technology nodes to provide hyper scaling and improved cost, power, power droop and reliability. Implemented new architectures to several AMD technology nodes that enabled true AMD hyper scaling. Several hundred million dollar ROI savings expected over technology lifetime. Proposed new architectures for future nodes for improved cell placment utilization, power drop and EM performance and taking full advantage of EUV patterning.
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Static Timing Risk Analysis Tool Development
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Developed a tool and graphical interface that could pull in multi-corner static timing simulation results and analyze or graph set up or hold timing risk based on margin and movement across multiple timing corners. It was written in Perl5 and Perl Tk.
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Yield and Qualification Test Chip Vehicle Design
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Designed and taped out several yield tile vehicles. Developed a front end of line and middle of line based vehicle which included tile based process module variants with emission and voltage contrast diagnostic capability and rapid fault isolation. Also developed a tile based back end of line vehicle which included bit map capability, rapid voltage contrast diagnosis and focused ion beam isolation capability. Also was the lead top level designer of a mixed signal qualification vehicle.
Honors & Awards
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2 Corporate Values Awards in 2006
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12 Employee Excellence Awards Throughout Career
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2006 FSA Fabless Semiconductor Award - DFM Hard Work and Excellence Achievement Award
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Employee retention programs
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Received key technical staff stay put retention incentives on 3 separate occasions thoughout 27 year career.
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Inventor of the Year Award in 2002
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Inventor of the Year Award in 2006
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Winners Circle Award in 2005
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