Siraj E Mubarak

By following a few simple but very effective steps, we can create a complex debug circuit that meets the stringent requirements of modern electronic systems today! While designing a high speed debug circuit, the selection of appropriate high speed debug interface is very critical. The usual debug interfaces like JTAG may not be suitable any more. Considering USB 3.0, PCIe, ethernet interface etc will be the way to go ahead. Bandwidth, latency, protocol overhead computations for each interface is very critical. If multiple (more than 1) clock domains are used , then having proper synchronization circuits like async fifo or handshake protocols are very vital. Using techniques like parallel processing, pipelining, retiming, and clock domain partitioning are equally important to meet timing. We should also allow support for dynamic reconfiguration to quickly adapt to the change in debug requirements. We should also provide enough heat sinks, thermal vias, and airflow to avoid overheating to take care of thermal management. Signal integrity checks must also be performed for high speed debug circuits to ensure there is no reflection , cross talk or signal degradation. 

6

As the trend of IP-based designs continues to grow, the demand for Verification Intellectual Properties (VIPs) has increased. VIPs are pre-defined functional blocks that can be inserted into testbenches for verifying a design, just like design IPs. Verification of large SOC designs takes more than 50% of the overall project life cycle, and it is done at multiple stages. Verifying smaller logical blocks, verifying a group of logic components at a sub-system level, and then verification of the entire SOC chip. VIP blocks can help in all these levels of verification as simulation models for the actual design IP. The VIP blocks usually consist of bus functional models, stimulus generators, protocol monitors, and functional coverage blocks. Since industry design testbenches follow different languages and methodologies, these VIPs are generally designed as configurable components that can be configured and easily integrated into different verification environments. #IPbaseddesigns #verificationIPs #SOCchip #VIPblocks #simulationmodels #busfunctionalmodels #protocolmonitors #functionalcoverageblocks #verificationenvironments Synopsys & Cadence are two of the biggest VIP vendors. There are four main user groups for VIP: 1. Developers of design IP for an emerging or existing specification 2. Early adopters and integrators 3. Subsystem developers 4. SoC developers

3

Following the ALU test, I tested the ROM module. This design features a 16-bit address input, three 8-bit data outputs (data1, data2, data3) for pipeline efficiency, and an integrated external address (EA) signal (ea_int) for seamless memory expansion. Verifying the ROM is a major step forward and will help me implement and validate the system even more. #FPGA #Microcontroller #EmbeddedSystems

6

𝑻𝒉𝒆 𝒄𝒐𝒎𝒑𝒍𝒆𝒙𝒊𝒕𝒚 𝒐𝒇 𝒎𝒐𝒅𝒆𝒓𝒏 𝒄𝒉𝒊𝒑 𝒅𝒆𝒔𝒊𝒈𝒏𝒔 𝒎𝒂𝒌𝒆𝒔 𝒊𝒕 𝒊𝒏𝒄𝒓𝒆𝒂𝒔𝒊𝒏𝒈𝒍𝒚 𝒅𝒊𝒇𝒇𝒊𝒄𝒖𝒍𝒕 𝒕𝒐 𝒎𝒂𝒏𝒂𝒈𝒆 𝒑𝒐𝒔𝒕-𝒔𝒊𝒍𝒊𝒄𝒐𝒏 𝒗𝒂𝒍𝒊𝒅𝒂𝒕𝒊𝒐𝒏 𝒘𝒊𝒕𝒉𝒊𝒏 𝒕𝒊𝒈𝒉𝒕 𝒑𝒓𝒐𝒋𝒆𝒄𝒕 𝒕𝒊𝒎𝒆𝒍𝒊𝒏𝒆𝒔. Adopting a robust Design for Debug (DFD) strategy can help manage this complexity more effectively. 𝐒𝐨𝐥𝐮𝐭𝐢𝐨𝐧: 𝘊𝘰𝘮𝘱𝘳𝘦𝘩𝘦𝘯𝘴𝘪𝘷𝘦 𝘔𝘰𝘯𝘪𝘵𝘰𝘳𝘪𝘯𝘨: DFD strategies provide detailed monitoring of chip performance, allowing for quick identification of issues. 𝘌𝘧𝘧𝘪𝘤𝘪𝘦𝘯𝘵 𝘛𝘳𝘰𝘶𝘣𝘭𝘦𝘴𝘩𝘰𝘰𝘵𝘪𝘯𝘨: Streamlined debugging processes enable faster troubleshooting and issue resolution. 𝘌𝘯𝘩𝘢𝘯𝘤𝘦𝘥 𝘗𝘦𝘳𝘧𝘰𝘳𝘮𝘢𝘯𝘤𝘦: Improved validation processes lead to higher performing, more reliable chips. 𝐊𝐞𝐲 𝐏𝐨𝐢𝐧𝐭𝐬: Managing post-silicon validation for complex chip designs is challenging. A robust DFD strategy enhances monitoring and troubleshooting. Efficient validation processes result in higher performing, reliable chips. 𝐂𝐚𝐥𝐥 𝐭𝐨 𝐀𝐜𝐭𝐢𝐨𝐧: Struggling with the complexity of post-silicon validation? Please explore how a robust DFD strategy can simplify your processes and improve chip performance. #DFD #ChipPerformance #SiliconValidation #TechSolutions #ChipDesign #DFD #SiliconValidation #TechInnovation  #vlsi #rfengineering #rfdesign #radiofrequency #fpga #fpgadesign  #verilog #verification #vhdl #embedded #embeddedsoftware #debugging  #synthesis #xilinx #DSP #systemverilog #uvm #systemsengineer #networking #ethernet #emulation #designverification #dv #physicaldesign #wireless #cloud #programmanagement #programmanager #designengineer #hardware #software #architect #cgm

11

𝐓𝐡𝐞 𝐄𝐯𝐨𝐥𝐮𝐭𝐢𝐨𝐧 𝐨𝐟 𝐃𝐞𝐬𝐢𝐠𝐧 𝐟𝐨𝐫 𝐃𝐞𝐛𝐮𝐠 (𝐃𝐅𝐃) 𝐎𝐯𝐞𝐫 𝐭𝐡𝐞 𝐃𝐞𝐜𝐚𝐝𝐞𝐬: 𝐀 𝐉𝐨𝐮𝐫𝐧𝐞𝐲 Design for Debug (DFD) has come a long way since its inception, evolving from a niche aspect of chip design to a critical component of modern electronics. This journey reflects the incredible advancements in technology and the relentless pursuit of perfection in the semiconductor industry. Let's take a walk through to see how DFD has evolved. 𝐓𝐡𝐞 𝐄𝐚𝐫𝐥𝐲 𝐃𝐚𝐲𝐬: 𝐁𝐚𝐬𝐢𝐜 𝐃𝐞𝐛𝐮𝐠𝐠𝐢𝐧𝐠 𝐓𝐞𝐜𝐡𝐧𝐢𝐪𝐮𝐞𝐬 In the early days of chip design, debugging was a straightforward but labor-intensive process. Engineers relied on basic techniques like signal probing and manual inspection to identify and fix issues. These methods, though effective at the time, were limited in scope and often resulted in lengthy development cycles. 𝐓𝐡𝐞 1980𝐬 𝐚𝐧𝐝 1990𝐬: 𝐄𝐦𝐞𝐫𝐠𝐞𝐧𝐜𝐞 𝐨𝐟 𝐒𝐭𝐫𝐮𝐜𝐭𝐮𝐫𝐞𝐝 𝐃𝐅𝐃 As chips grew more complex, the need for more sophisticated debugging methods became apparent. The 1980s and 1990s saw the emergence of structured DFD approaches. Built-in Self-Test (BIST) mechanisms were introduced, allowing for automated testing of certain chip functions. This era also saw the development of boundary scan techniques, to test interconnects on PCB's. 𝐓𝐡𝐞 2000𝐬: 𝐈𝐧𝐭𝐞𝐠𝐫𝐚𝐭𝐢𝐨𝐧 𝐰𝐢𝐭𝐡 𝐃𝐞𝐬𝐢𝐠𝐧 𝐀𝐮𝐭𝐨𝐦𝐚𝐭𝐢𝐨𝐧 The turn of the millennium brought significant advancements in design automation tools. DFD started to integrate more deeply with these tools, leading to more automated and efficient debugging processes. Enhanced scan techniques, such as Scan Compression, were developed to reduce the amount of test data and improve fault coverage. 𝐓𝐡𝐞 2010𝐬: 𝐑𝐢𝐬𝐞 𝐨𝐟 𝐀𝐝𝐯𝐚𝐧𝐜𝐞𝐝 𝐃𝐅𝐃 𝐓𝐞𝐜𝐡𝐧𝐢𝐪𝐮𝐞𝐬 The 2010s were characterized by rapid advancements in chip complexity and performance requirements. Advanced DFD techniques, such as on-chip debug infrastructures and embedded logic analyzers, became essential. These innovations allowed for real-time monitoring and debugging of complex systems. 𝐓𝐨𝐝𝐚𝐲: 𝐓𝐡𝐞 𝐀𝐠𝐞 𝐨𝐟 𝐀𝐈 𝐚𝐧𝐝 𝐌𝐚𝐜𝐡𝐢𝐧𝐞 𝐋𝐞𝐚𝐫𝐧𝐢𝐧𝐠 𝐢𝐧 𝐃𝐅𝐃 Today, DFD is at the forefront of technological innovation, leveraging the power of AI and machine learning. AI-driven tools can analyze vast amounts of data from chip operations, providing insights that were previously impossible to obtain. 𝐋𝐨𝐨𝐤𝐢𝐧𝐠 𝐀𝐡𝐞𝐚𝐝: The Future of DFD DFD will continue to evolve, driven by the increasing complexity of semiconductor devices. Emerging technologies, such as quantum computing and neuromorphic chips, will present new challenges and opportunities for DFD. As we continue to innovate and push the limits of technology, DFD will remain a cornerstone of our success. Understanding its evolution helps us appreciate the progress we’ve made and inspires us to tackle the challenges ahead. #Semiconductor #DFD #Innovation #ChipDesign #FutureOfTech

8

2 Comments

A7908-M2 is a Multi-Band LTE-FDD/LTE-TDD/HSPA+ module which supports Category 6 with CA and MIMO.  With a rich protocols, it is integrated with interfaces such as PCIe, USB3.0, GPIO etc. This module provides applications with great flexibility and ability of integration. A7908-M2 adopts M2 form factor. AT commands of A7908- M2 are compatible with SIM79XX series modules. This also minimizes costs for customer and shortens time to market. It is designed for applications that need huge data transmission in various wireless situations. Due to its high efficiency, security and flexibility, this module suits various applications. #a7908 #4g #lte #4gmodule #ltemodule #wireless #iot #module #modem #4gmodem #m2 #cat6

5

Paging in memory subsystem: Paging is a memory management scheme that eliminates the need for contiguous allocation of physical memory, thereby minimizing fragmentation and allowing more efficient use of available memory resources. 👉 Basic Concepts in Paging 1️⃣ Pages and Frames Pages: The virtual memory is divided into fixed-size blocks called pages. These are typically 4KB in size, though sizes can vary. Frames: The physical memory is similarly divided into fixed-size blocks called frames, which are the same size as pages. 2️⃣ Page Table: A data structure used to keep track of the mapping between virtual pages and physical frames. Each process has its own page table, which translates virtual addresses to physical addresses. 3️⃣ Page Table Entry: Each entry in the page table contains information about a specific virtual page, including the frame number it maps to, access permissions, and status bits (e.g., present, modified). ✅ Components Involved in Paging 1️⃣ Memory Management Unit (MMU): The MMU is a hardware component that handles the translation of virtual addresses to physical addresses, utilizing the page table and TLB (Translation Lookaside Buffer). 2️⃣ Translation Lookaside Buffer (TLB): A cache used by the MMU to speed up address translation by storing recent translations of virtual addresses to physical addresses. If a virtual address is found in the TLB (TLB hit), translation is fast. If not (TLB miss), the page table must be consulted. 3️⃣ Page Tables: Each process has its own page table, managed by the operating system. The page table contains entries for each page in the virtual address space, mapping them to physical frames. 👉 Paging Mechanisms 1️⃣ Single-Level Paging: The simplest form of paging where a single page table is used for address translation. Suitable for small address spaces but inefficient for large address spaces due to large page tables. 2️⃣ Multi-Level Paging: Hierarchical paging where the page table is divided into multiple levels. This reduces the memory overhead for page tables in large address spaces. 3️⃣ Inverted Page Table: A global page table that contains one entry for each frame of physical memory, mapping physical addresses to virtual addresses. It reduces the size of the page table but can be slower due to the need for searching. 🌟 Benefits of Paging 1️⃣ Efficient Memory Use: Paging allows non-contiguous allocation of physical memory, reducing fragmentation and making better use of available memory. 2️⃣ Isolation and Protection: Each process operates in its own virtual address space, isolated from others, enhancing security and stability. 3️⃣ Scalability: Paging supports large virtual address spaces, allowing modern operating systems to manage memory for multiple processes efficiently. 4️⃣ Ease of Allocation: Fixed-size pages and frames simplify memory allocation and deallocation, as any free frame can satisfy a page request. Credit : Gopal Chakraborty #memory #embedded #vlsiforall

24

𝐓𝐫𝐚𝐧𝐬𝐟𝐨𝐫𝐦𝐢𝐧𝐠 𝐄𝐭𝐡𝐞𝐫𝐧𝐞𝐭 𝐢𝐧𝐭𝐨 𝐓𝐒𝐍: 𝐓𝐡𝐞 𝐁𝐚𝐜𝐤𝐛𝐨𝐧𝐞 𝐨𝐟 𝐑𝐞𝐚𝐥-𝐓𝐢𝐦𝐞, 𝐑𝐞𝐥𝐢𝐚𝐛𝐥𝐞 𝐂𝐨𝐧𝐧𝐞𝐜𝐭𝐢𝐯𝐢𝐭𝐲: 𝘐𝘯 𝘵𝘩𝘦 𝘸𝘰𝘳𝘭𝘥 𝘰𝘧 𝘯𝘦𝘵𝘸𝘰𝘳𝘬𝘪𝘯𝘨, 𝘌𝘵𝘩𝘦𝘳𝘯𝘦𝘵 𝘪𝘴 𝘵𝘩𝘦 𝘣𝘢𝘤𝘬𝘣𝘰𝘯𝘦 𝘵𝘩𝘢𝘵 𝘱𝘰𝘸𝘦𝘳𝘴 𝘦𝘷𝘦𝘳𝘺𝘵𝘩𝘪𝘯𝘨 𝘧𝘳𝘰𝘮 𝘩𝘰𝘮𝘦 𝘪𝘯𝘵𝘦𝘳𝘯𝘦𝘵 𝘵𝘰 𝘤𝘰𝘮𝘱𝘭𝘦𝘹 𝘪𝘯𝘥𝘶𝘴𝘵𝘳𝘪𝘢𝘭 𝘴𝘺𝘴𝘵𝘦𝘮𝘴. 𝘉𝘶𝘵 𝘢𝘴 𝘵𝘩𝘦 𝘥𝘦𝘮𝘢𝘯𝘥𝘴 𝘧𝘰𝘳 𝘳𝘦𝘢𝘭-𝘵𝘪𝘮𝘦, 𝘳𝘦𝘭𝘪𝘢𝘣𝘭𝘦 𝘤𝘰𝘮𝘮𝘶𝘯𝘪𝘤𝘢𝘵𝘪𝘰𝘯 𝘨𝘳𝘰𝘸, 𝘦𝘴𝘱𝘦𝘤𝘪𝘢𝘭𝘭𝘺 𝘪𝘯 𝘢𝘶𝘵𝘰𝘮𝘰𝘵𝘪𝘷𝘦 𝘢𝘯𝘥 𝘪𝘯𝘥𝘶𝘴𝘵𝘳𝘪𝘢𝘭 𝘢𝘱𝘱𝘭𝘪𝘤𝘢𝘵𝘪𝘰𝘯𝘴, 𝘌𝘵𝘩𝘦𝘳𝘯𝘦𝘵 𝘯𝘦𝘦𝘥𝘴 𝘢𝘯 𝘶𝘱𝘨𝘳𝘢𝘥𝘦. 𝐓𝐡𝐞 𝐄𝐯𝐨𝐥𝐮𝐭𝐢𝐨𝐧 𝐨𝐟 𝐄𝐭𝐡𝐞𝐫𝐧𝐞𝐭 𝐭𝐨 𝐓𝐒𝐍: 𝘗𝘳𝘦𝘤𝘪𝘴𝘪𝘰𝘯 𝘛𝘪𝘮𝘪𝘯𝘨: One of the foundational changes TSN brings to Ethernet is precision time synchronization. By using IEEE 802.1AS, TSN ensures that all devices on the network are synchronized to within nanoseconds. This is crucial for applications like automotive systems where timing is critical. 𝘛𝘳𝘢𝘧𝘧𝘪𝘤 𝘚𝘤𝘩𝘦𝘥𝘶𝘭𝘪𝘯𝘨: TSN introduces sophisticated traffic scheduling (IEEE 802.1Qbv), allowing critical data packets to be prioritized and transmitted at precisely scheduled times. This ensures that important information, like sensor data in a car, is never delayed or lost. 𝘚𝘵𝘳𝘦𝘢𝘮 𝘙𝘦𝘴𝘦𝘳𝘷𝘢𝘵𝘪𝘰𝘯: With TSN’s stream reservation protocols (IEEE 802.1Qat), network resources are reserved for critical data streams, guaranteeing bandwidth and reducing the risk of congestion. This is vital for ensuring smooth and uninterrupted operation in high-demand environments. 𝘌𝘯𝘩𝘢𝘯𝘤𝘦𝘥 𝘙𝘦𝘭𝘪𝘢𝘣𝘪𝘭𝘪𝘵𝘺: TSN enhances Ethernet’s reliability with redundancy protocols (IEEE 802.1CB), enabling seamless failover and reducing the risk of data loss. This is especially important in safety-critical applications like autonomous driving. Imagine a world where your car can communicate with traffic lights, other vehicles, and even pedestrians in real-time, ensuring a safer and more efficient journey. This vision relies on TSN’s ability to handle these complex, time-sensitive communications. 𝐌𝐚𝐤𝐢𝐧𝐠 𝐈𝐭 𝐏𝐞𝐫𝐬𝐨𝐧𝐚𝐥: Every time you drive your car, work in a high-tech factory/advanced medical devices, TSN is likely at work behind the scenes. It’s the invisible technology ensuring that all these systems communicate flawlessly, keeping you safe and enhancing your experience. Is this useful? Do you want to add anything? Please let me know. #Networking #TSN #Ethernet #AutomotiveInnovation #IndustrialAutomation #FutureOfTech #ChipDesign #DFD #SiliconValidation #TechInnovation #vlsi #rfengineering #rfdesign #radiofrequency #fpga #verilog #verification #vhdl #embedded #debugging  #synthesis #xilinx #DSP #systemverilog #uvm #systemsengineer #networking #ethernet #emulation #designverification #dv #physicaldesign #wireless #cloud #programmanagement  #programmanager #designengineer #hardware #software #architect #cgm

5

How to Choose the Right EDA Tool Between Synopsys, Cadence & Siemens for Your Next Project 🚀 Synopsys: Strengths: Digital Design: Industry leader in logic synthesis (Design Compiler) with excellent performance and power optimization capabilities. Verification: Offers VCS, a powerful simulation tool with good scalability and advanced debugging features. Formal Verification: Offers Formality, a leading tool for formally verifying chip designs to ensure they meet functional specifications. IP Cores: Provides a wide range of pre-designed and pre-verified intellectual property (IP) cores that can be integrated into your chip design, saving time and resources. Weaknesses: Layout: While Synopsys offers place and route tools (IC Compiler), Cadence might have a slight edge in this area. Analog/Mixed-Signal: While competitive solutions exist (Custom Compiler), Cadence's Virtuoso suite might be more established. 🚀 Cadence: Strengths: Layout: Offers industry-leading place and route tools known for their speed, efficiency, and advanced capabilities for complex designs. Analog/Mixed-Signal: Virtuoso suite is widely recognized as the gold standard for analog/mixed-signal design, offering a rich set of tools for schematic capture, simulation, layout, and verification. Custom Design: Strong focus on custom design flows, with tools specifically designed for high-performance and low-power applications. Weaknesses: Cost: Can be more expensive compared to Synopsys for some tools, particularly for perpetual licenses. Learning Curve: Cadence tools can have a steeper learning curve compared to Synopsys, especially for new users. 🚀 Siemens EDA (formerly Mentor Graphics): Strengths: Value: Often offers a more cost-effective option compared to Synopsys and Cadence, particularly for smaller design teams or less complex projects. Breadth of Tools: Provides a comprehensive suite of tools covering most aspects of the design flow, from RTL design to physical design. Hardware Description Languages (HDLs): Offers QuestaSim, a popular simulator that supports multiple HDLs like Verilog, VHDL, and SystemVerilog. Weaknesses: Market Share: May not be as dominant in specific areas like synthesis or verification compared to Synopsys and Cadence. Support: Support infrastructure might be less extensive compared to the bigger players. A detailed post is in comments (with examples)

316

3 Comments

If you are attending any embedded system training, Make sure you do few unique projects yourself as well. Don't depend on the well known project of institute which was done by hundreds in the past. Just check project mentioned in LinkedIn profile of your alumni. We have covered up to Systick for May regular developer kit batch. Similar progress is with weekend as well. Now additional experiments on clocking architecture will be done today. We will also discus first mini-project based on learning so far. We have moved Thumb programming to last. Currently we have Saturday slot available for Developer kit and Linux Application development. Weekday morning slots are planned for college students where semester break already started. Engineering students should try their C skills with industry tools. https://lnkd.in/g2wT48q7 #embedded #embedkari #opentowork #firmware #iot #freshers

3

2 Comments

Excited to share our recently launched FPGA-based AVR board, designed to revolutionize defence, renewable energy, industrial automation, and telecommunications. The board has been rigorously tested and excels in voltage regulation, comprehensive monitoring, dual voltage support (28 V DC and 270 V DC), and robust communication interfaces (CAN, Ethernet, IPMS). Leveraging powerfull #AMD FPGA, it ensures real-time processing, unmatched precision, and seamless adaptability, making it the perfect solution for advanced automatic voltage regulation in the most demanding applications. Kudos to our Talented engineers and researchers !!!! Stay tuned for more innovative breakthroughs!!!!!! #deeptech #vanix #startup #madinindia #TechInnovation #FPGA #AMD #VoltageRegulation #IndustrialAutomation #Telecommunications #RenewableEnergy #DefenceTechnology #RealTimeProcessing #AdvancedTechnology #SmartTech #IoT #Automation #Engineering #Innovation #TechBreakthrough #FutureTech #HighPrecision #EmbeddedSystems #Electronics

12

2 Comments

🔬 Advanced Node Challenges: Navigating the Next Frontier 🔬 As we push towards advanced nodes like 5nm and beyond, the semiconductor industry faces significant challenges. From managing increased power density to ensuring manufacturability and reliability, each new node presents unique hurdles. Innovative solutions in design and verification are crucial to overcoming these barriers and achieving the performance gains promised by advanced nodes. What challenges have you encountered with advanced nodes? #Semiconductors #AdvancedNodes #DigitalDesign #Verification #Innovation

3

Is Intel Corporation the new Kodak? Over the past decades, Intel has missed significant opportunities in the processor market, particularly for smartphones and tablets. Today, it holds a minimal role in AI and is losing ground in data centers. Intel also lost Apple’s MAC computer business. Recently, a new trend has emerged with AI-enabled laptops using Qualcomm and NVIDIA setups. What’s left for Intel? Is its future as a pure foundry? Can it catch up with likes of TSMC and Samsung Semiconductor? Or will it resurface as a major player in any of the processor sectors? #AI #Semiconductor #Smartphone #Datacenter #Kodak #processor

22

1 Comment

people pondering why we don't have 128bit systems in reality a huge number of "computers" being shipped annually, possibly a majority, isn't even 64 bits vast majority of microcontrollers are 32 bit or less and even in a number of 64 bit applications (which the computer industry went to mainly because 32bit could only address 4GB) where custom buses can be designed, address buses are often 48 or 56 bits (and even those can't be fully utilised, just that the architects over-provision) even in very large compute systems the arithmetic also rarely uses 64 bit directly (float in C is 32 bits; to get to 64 you need to use double; it is useful but relatively infrequently), so data bus width of 64 is useful because more parallel wires allow faster bandwidth for packetized data on Network-on-chip (or fabric), and as far as the data bus width is concerned, that is in fact very often larger than 64 bits ( even if the address space is less than 64 bits) in other words, vast majority of computers aren't really 64bits even today in any meaningful sense. just that people don't know about those computers https://lnkd.in/dhFrhVb2

21

8 Comments

With the increasing complexity of design and the popular adoption of IP cores, module placement has become more important than ever before. In VLSI physical design, module placement is one of the main tasks of floorplanning at the early stage. Hard IP cores, which usually have fixed area and shape, are regarded as hard modules at the placement stage. While several placement algorithms exist, most automatic placers are developed for standard cells. However, there are still some disadvantages for these automatic placers to place the hard IP cores. A new hard IP core placement method is proposed here, which takes into consideration critical issues such as power, connection of pre-placed hard IP cores with standard cells, location of pins and halo, and size variation of hard IP cores. This method combines automatic placement with manual adjustments such as rotation and overlap resolving, resulting in optimized hard IP core placement. Read more about this hard IP core placement method along with the figure below. hashtag #VLSI hashtag #PhysicalDesign hashtag #IPCorePlacement For an actual VLSI design, which is viewed as a set of hard IP cores and soft modules according to the hierarchy at the module placement stage, the automatic placer might not produce good results because of certain factors. The main reason is that the location of hard IP cores usually has a priority. These modules are pre-placed or placed inside soft modules, and then the standard cells are subject to be placed in the rest area of relative soft modules. As a result, the connectivity between the standard cells and the hard IP cores will not be taken into consideration and the power routing plan is more complicated because the power grids will be broken by the presence of these modules, which make the IR drop more serious. In addition, the shape and the location of pins of hard IP cores are varied with the foundry. And the overlap of the halos is difficult to be treated with due to the different values of the halo. In order to solve the problems mentioned above, here is a a hard IP core placement method, which does efficient manual adjustments based on the initial automatic placement of hard IP cores, as the Figure shows. Only the steps relating to the hard IP core placement are drawn and connected in the figure. The manual adjustment mainly includes two styles. One is change the location slightly, such as rotation and removing overlap. The other is to change the location obviously after the following steps in physical design, such as power routing, standard cells placement and routing.

2

New ASIC Verification Courses Available Online and Offline with Guaranteed Placement Assistance

11

What are considered parasitic junctions in core analog layout, can be silicon saving junctions when it comes to ESD robustness. It’s often these hidden junctions that we don’t usually consider in day to day layout, that become the backbones of our ESD strategies. This is the sort of detail that we discuss during our ESD layout course; the next one of which, runs from Tuesday 21st May, through Friday 24th, delivered remotely. If you’re interested in participating or hearing more, please have your manager or HR department reach out to James Telfer for information on pricing and availability.

43

15 Comments

DSPs are processors/microcomputers whose hardware, software, and instruction sets are optimized for high-speed numeric processing applications  for processing digital data representing analog signals in real time. Signals are converted from time domain to the frequency domain through use of the Fourier transform. The Fourier transform converts the time information to a magnitude and phase component of each frequency. With some applications, how the phase varies with frequency can be a significant consideration. Where phase is unimportant, often the Fourier transform is converted to the power spectrum, which is the magnitude of each frequency component squared. Digital signal processing algorithms are usually built up from three basic functions: Add, Multiply, and Delay. The functions are applied in combination to build up complex algorithms in discrete time systems. The Multiply and Add functions are known as operations or ops. Digital signal processing is more flexible because DSP operations can be altered using digitally programmable systems. Digital signal processing is more secure because digital information can be easily encrypted and compressed. Signal processing involves converting or transforming data in a way that allows us to see things in it that are not possible via direct observation. Signal processing allows engineers and scientists to analyze, optimize, and correct signals, including scientific data, audio streams, images, and video. In the context of digital signal processing (DSP), a digital signal is a discrete time, quantized amplitude signal. Signal processing is an electrical engineering subfield that focuses on analyzing, modifying and synthesizing signals, such as sound, images, potential fields, seismic signals, altimetry processing, and scientific measurements.

6