Timeline for Is the L3 cache shared by all cores for a Sandy-Bridge E Xeon CPU?
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| Jul 11, 2015 at 4:17 | comment | added | Peter Cordes | L2 and L3 are not at all the same thing. On recent Intel designs, L1/L2 are per-core and small (32k L1 I$ & D$ / 256k unified L2), while L3 is inclusive and shared by the GPU and all cores. L1/L2 are physically separate, but kind of serve similar purposes (i.e. making memory access fast for a single core). The inclusive L3 has another purpose: coherency between cores (and the GPU). See @DavidSchwartz's answer. | |
| Apr 17, 2012 at 19:11 | history | edited | Stephen R | CC BY-SA 3.0 |
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| Apr 16, 2012 at 22:05 | history | answered | Stephen R | CC BY-SA 3.0 |