We have been [waiting][1] for Verilog and SystemVerilog (SV) highlighting for a long time. Apparently we will have Verilog support with *highlight.js*, but SV will continue to be unsupported. Still much better than before. I'm happy with the change and appreciate your effort. Let me put some Verilog code (from [highlight.js demo][2]) here to see the result after the roll-out. I assume the language code will be `lang-verilog`. ```lang-verilog `timescale 1ns / 1ps /** * counter: a generic clearable up-counter */ module counter #(parameter WIDTH=64, NAME="world") ( input clk, input ce, input arst_n, output reg [WIDTH-1:0] q ); string name = "counter"; localparam val0 = 12'ha1f; localparam val1 = 12'h1fa; localparam val2 = 12'hfa1; // some child clock_buffer #(WIDTH) buffer_inst ( .clk(clk), .ce(ce), .reset(arst_n) ); // Simple gated up-counter with async clear always @(posedge clk or negedge arst_n) begin if (arst_n == 1'b0) begin q <= {WIDTH {1'b0}}; end else begin q <= q; if (ce == 1'b1) begin q <= q + 1; end end end function int add_one(int x); return x + 1; endfunction : add_one `ifdef SIMULATION initial $display("Hello %s", NAME); `endif endmodule : counter class my_data extends uvm_data; int x, y; function add_one(); x++; y++; endfunction : add_one endclass : my_data ``` [1]: https://meta.stackexchange.com/questions/284072/create-verilog-syntax-highlighter [2]: https://highlightjs.org/static/demo/