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According to the question Enable Verilog syntax highlighting, it is clear how to enable the syntax for various languages. That is not what this question is about, nor is it a duplicate of that. Additionally, this question was asked, about Verilog syntax highlighting, a couple of years back and was closed as duplicate of the aforementioned one. Basically my question follows on from that.

On EE.SE, we are getting more and more frequently questions regarding Verilog (I tend to answer many of them), however as was mentioned in the comments of the closed question, it seems there is a lack of a highlighting scheme for Verilog and/or SystemVerilog. There is one for VHDL, but that is too different to be applicable.

As a result we end up with lots of questions and answers with code which ends up either lacking any highlighting at all, or highlights random words depending on what tag is used, and trying to do something like <!-- language: lang-verilog -->, clearly results in random highlight as well as there is no defined language. This I see as a problem as it makes the code less readable - I end up having to copy it into something like NP++ to get it to be highlighted.

It's been 2 years since that other question was closed, and nothing has changed.

After looking around, there is a SystemVerilog parser for Google Code Prettify. It's currently sitting as an open pull request and hasn't yet been pulled into the main repository.

Hopefully this can be used for highlighting on SE. A SystemVerilog parser will also work perfectly well for Verilog as well.

Any thoughts on whether this can be implemented?

If it needs to be merged I can prod the folk on the github repository to look at pulling it the parser. It's been a further 6 months since I asked the question and no progress has been made so far as I can see (still no Verilog syntax highlighting on EE.SE).

According to the question Enable Verilog syntax highlighting, it is clear how to enable the syntax for various languages. That is not what this question is about, nor is it a duplicate of that. Additionally, this question was asked, about Verilog syntax highlighting, a couple of years back and was closed as duplicate of the aforementioned one. Basically my question follows on from that.

On EE.SE, we are getting more and more frequently questions regarding Verilog (I tend to answer many of them), however as was mentioned in the comments of the closed question, it seems there is a lack of a highlighting scheme for Verilog and/or SystemVerilog. There is one for VHDL, but that is too different to be applicable.

As a result we end up with lots of questions and answers with code which ends up either lacking any highlighting at all, or highlights random words depending on what tag is used, and trying to do something like <!-- language: lang-verilog -->, clearly results in random highlight as well as there is no defined language. This I see as a problem as it makes the code less readable - I end up having to copy it into something like NP++ to get it to be highlighted.

It's been 2 years since that other question was closed, and nothing has changed.

After looking around, there is a SystemVerilog parser for Google Code Prettify. It's currently sitting as an open pull request and hasn't yet been pulled into the main repository.

Hopefully this can be used for highlighting on SE. A SystemVerilog parser will also work perfectly well for Verilog as well.

Any thoughts on whether this can be implemented?

If it needs to be merged I can prod the folk on the github repository to look at pulling it the parser. It's been a further 6 months since I asked the question and no progress has been made so far as I can see (still no Verilog syntax highlighting on EE.SE).

According to the question Enable Verilog syntax highlighting, it is clear how to enable the syntax for various languages. That is not what this question is about, nor is it a duplicate of that. Additionally, this question was asked, about Verilog syntax highlighting, a couple of years back and was closed as duplicate of the aforementioned one. Basically my question follows on from that.

On EE.SE, we are getting more and more frequently questions regarding Verilog (I tend to answer many of them), however as was mentioned in the comments of the closed question, it seems there is a lack of a highlighting scheme for Verilog and/or SystemVerilog. There is one for VHDL, but that is too different to be applicable.

As a result we end up with lots of questions and answers with code which ends up either lacking any highlighting at all, or highlights random words depending on what tag is used, and trying to do something like <!-- language: lang-verilog -->, clearly results in random highlight as well as there is no defined language. This I see as a problem as it makes the code less readable - I end up having to copy it into something like NP++ to get it to be highlighted.

What is the procedure to go about creating a definition or extension for parsing Verilog? (both for EE.SE and probably SO as well as Verilog questions appear on there with regularity as well).

It's been 2 years since that other question was closed, and nothing has changed.

If it requires someone to make the a js file like the ones linked to in the first question I posted a link to, I am happy to try to build one if there is any readme as to the syntax of that file.

After looking around, there is a SystemVerilog parser for Google Code Prettify. It's currently not been pulled into the main repository though.

Hopefully this can be used for highlighting on SE. A SystemVerilog parser will also work ok for Verilog as well (at the very least it will be a darn sight better than no highlighting at all).

According to the question Enable Verilog syntax highlighting, it is clear how to enable the syntax for various languages. That is not what this question is about, nor is it a duplicate of that. Additionally, this question was asked, about Verilog syntax highlighting, a couple of years back and was closed as duplicate of the aforementioned one. Basically my question follows on from that.

On EE.SE, we are getting more and more frequently questions regarding Verilog (I tend to answer many of them), however as was mentioned in the comments of the closed question, it seems there is a lack of a highlighting scheme for Verilog and/or SystemVerilog. There is one for VHDL, but that is too different to be applicable.

As a result we end up with lots of questions and answers with code which ends up either lacking any highlighting at all, or highlights random words depending on what tag is used, and trying to do something like <!-- language: lang-verilog -->, clearly results in random highlight as well as there is no defined language. This I see as a problem as it makes the code less readable - I end up having to copy it into something like NP++ to get it to be highlighted.

It's been 2 years since that other question was closed, and nothing has changed.

After looking around, there is a SystemVerilog parser for Google Code Prettify. It's currently sitting as an open pull request and hasn't yet been pulled into the main repository.

Hopefully this can be used for highlighting on SE. A SystemVerilog parser will also work perfectly well for Verilog as well.

Any thoughts on whether this can be implemented?

If it needs to be merged I can prod the folk on the github repository to look at pulling it the parser. It's been a further 6 months since I asked the question and no progress has been made so far as I can see (still no Verilog syntax highlighting on EE.SE).

According to the question Enable Verilog syntax highlighting, it is clear how to enable the syntax for various languages. That is not what this question is about, nor is it a duplicate of that. Additionally, this question was asked, about Verilog syntax highlighting, a couple of years back and was closed as duplicate of the aforementioned one. Basically my question follows on from that.

On EE.SE, we are getting more and more frequently questions regarding Verilog (I tend to answer many of them), however as was mentioned in the comments of the closed question, it seems there is a lack of a highlighting scheme for Verilog and/or SystemVerilog. There is one for VHDL, but that is too different to be applicable.

As a result we end up with lots of questions and answers with code which ends up either lacking any highlighting at all, or highlights random words depending on what tag is used, and trying to do something like <!-- language: lang-verilog -->, clearly results in random highlight as well as there is no defined language. This I see as a problem as it makes the code less readable - I end up having to copy it into something like NP++ to get it to be highlighted.

What is the procedure to go about creating a definition or extension for parsing Verilog? (both for EE.SE and probably SO as well as Verilog questions appear on there with regularity as well).

It's been 2 years since that other question was closed, and nothing has changed.

If it requires someone to make the a js file like the ones linked to in the first question I posted a link to, I am happy to try to build one if there is any readme as to the syntax of that file.

According to the question Enable Verilog syntax highlighting, it is clear how to enable the syntax for various languages. That is not what this question is about, nor is it a duplicate of that. Additionally, this question was asked, about Verilog syntax highlighting, a couple of years back and was closed as duplicate of the aforementioned one. Basically my question follows on from that.

On EE.SE, we are getting more and more frequently questions regarding Verilog (I tend to answer many of them), however as was mentioned in the comments of the closed question, it seems there is a lack of a highlighting scheme for Verilog and/or SystemVerilog. There is one for VHDL, but that is too different to be applicable.

As a result we end up with lots of questions and answers with code which ends up either lacking any highlighting at all, or highlights random words depending on what tag is used, and trying to do something like <!-- language: lang-verilog -->, clearly results in random highlight as well as there is no defined language. This I see as a problem as it makes the code less readable - I end up having to copy it into something like NP++ to get it to be highlighted.

What is the procedure to go about creating a definition or extension for parsing Verilog? (both for EE.SE and probably SO as well as Verilog questions appear on there with regularity as well).

It's been 2 years since that other question was closed, and nothing has changed.

If it requires someone to make the a js file like the ones linked to in the first question I posted a link to, I am happy to try to build one if there is any readme as to the syntax of that file.

After looking around, there is a SystemVerilog parser for Google Code Prettify. It's currently not been pulled into the main repository though.

Hopefully this can be used for highlighting on SE. A SystemVerilog parser will also work ok for Verilog as well (at the very least it will be a darn sight better than no highlighting at all).