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An efficient hardware accelerator for NTT-based polynomial multiplication using FPGA

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Abstract

The number theoretic transform (NTT) is used to efficiently execute polynomial multiplication. It has become an important part of lattice-based post-quantum methods and the subsequent generation of standard cryptographic systems. However, implementing post-quantum schemes is challenging since they rely on intricate structures. This paper demonstrates how to develop a high-speed NTT multiplier highly optimized for FPGAs with few logical resources. We describe a novel architecture for NTT that leverages unique precomputation. Our method efficiently maps these specific pre-computed values into the built-in Block RAMs, which greatly reduces the area and time required for implementation when compared to previous works. We have chosen Kyber parameters to implement the proposed architectures. Compared to the most well-known approach for implementing Kyber’s polynomial multiplication using NTT, the AC (area \(\times \) latency) is reduced by \(33\%\), and AT (area \(\times \) time) is improved by \(18\%\) as a result of the pre-computation we suggest in this study.

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Authors and Affiliations

  1. Faculty of Computer Science and Engineering, Shahid Beheshti University, Tehran, Iran

    Raziyeh Salarifard

  2. Cyber Research Center, Shahid Beheshti University, Tehran, Iran

    Hadi Soleimany

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  1. Raziyeh Salarifard
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  2. Hadi Soleimany
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Raziyeh Salarifard and Hadi soleimany wrote the main manuscript, prepared figures and tables, and reviewed the manuscript.

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Correspondence to Raziyeh Salarifard.

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Salarifard, R., Soleimany, H. An efficient hardware accelerator for NTT-based polynomial multiplication using FPGA. J Cryptogr Eng 14, 415–426 (2024). https://doi.org/10.1007/s13389-024-00357-1

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