All Questions
Tagged with ltspice power-electronics
44
questions
2
votes
1
answer
86
views
Simulation problem in half bridge leg of an inverter
I am simulating Half Bridge Leg on an inverter. From the simulation, I could not understand why I was not getting proper dead time between high and low side fets. However, I set a delay time of 150ns ...
- 31
1
vote
1
answer
54
views
How to interpret Ids of low-side FET in phase leg configuration?
I am simulating a phase leg configuration as shown below using a [GS66508T][1] GaN FET. Does anyone know if the circuit is working correctly according to the current plot?
There is current spike above ...
user369787
1
vote
1
answer
38
views
LTspice parameters
I want to know how the .mod/.lib files in Ltspice are created by manufacturers. Let's say we have a Common Mode Choke (CMC). It will have some parameters as per its equivalent model at different freq ...
- 275
1
vote
1
answer
80
views
Slow simulation on LTspice
What could be the reason for the slow simulation speed for this converter circuit I have emulated from Fig 9-5: https://www.ti.com/lit/ds/symlink/lm5145.pdf?ts=1710376974553
- 275
1
vote
1
answer
75
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IR2110 LTspice high-side switching problem
I am working on a half-bridge simulation in LTspice. For the gate drive circuit I am working with an IR2110. My problem is that whatever I select Vin to be above 200 V output, it can't pass 200 V.
I ...
- 27
0
votes
1
answer
65
views
Simulation time for Full bridge
This is a full bridge circuit which I am trying to simulate in Ltspice with a snubber. When I use ideal switches instead of MOSFETS, the simulation works fine. But when I use the real mosfet models, ...
- 275
2
votes
1
answer
98
views
How would I create an analog block function in LTSpice?
I'm trying to create a small-signal model of a PSFB converter in LTSpice. The blocks in red are what I am trying to create, essentially a multiplier block which computes various .PARAM parameters that ...
- 73
1
vote
0
answers
46
views
Power Inverter Weird Output
I'm simulating a power inverter using Analog Devices LT1158IN#PBF as half bridge driver. This is the circuit I'm simulating:
Here is the plot of R1 and V9:
Seems like the voltage spikes over 20V ...
- 195
1
vote
0
answers
182
views
Flyback converter simulation in LTspice: discrepancy between Switching model and Averaged Switch model
I´m trying to make a Averaged Switch Model of a flyback converter for transient and AC simulation in LTspice. I´m following the document "Advances in Averaged Switch Modeling and Simulation" ...
- 11
1
vote
0
answers
87
views
Too few nodes error after running the simulation
What does "too few nodes" mean in this circuit? Any connection error? If it is some library error, please help with the solution.
- 275
2
votes
1
answer
333
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Small Signal Model of Two-Switch Forward - Basso
I've designed a two-switch forward converter, that I would like to create a small signal model for to examine the stability criteria of the converter and then compatibility with the EMI filter...
A ...
- 21
6
votes
1
answer
892
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Would this 3-phase sequence detector circuit work?
I was searching for a circuit that would detect 3 phase sequence and give dry contact output if the sequence is correct.
I have found the schematic below, from a Daikin compressor manual. I wonder if ...
- 81
2
votes
2
answers
2k
views
How do switches work in ltspice?
I Have set up my switch according to the rules specified, using the dot command to determine the behavior of the switch but I still get the error.
"Can't find definition of model 'S1'"
I ...
- 29
4
votes
2
answers
3k
views
LTspice Frequency Response Analyzer (FRA)
This post is a continuation of this question.
LTspice recently introduced a new feature called frequency response analyzer, see the image below.
The green box shows the symbol for FRA. If you click ...
- 2,593
6
votes
2
answers
974
views
How to measure the stability of a buck converter using LTspice
Below is my buck converter circuit. How can I check its stability using LTspice?
I need to measure GM and PM.
Is this true that a 30–60 degrees phase margin and a gain margin of 2–10 dB are desirable ...
- 2,593