All Questions
7
questions
0
votes
1
answer
246
views
What is the role of master clock speed on DAC?
In the I2S protocol we have 3 signal + one none-standard master clock (mentioned by Olin Lathrop):
data
LRCK/FCK (frame synchronizer)
BCK (bit clock)
MCK/SCK (master clock)
Question 1: Why do we ...
- 551
0
votes
1
answer
406
views
switching between multiple clock (I2S, audio)
I'm trying to draw a schematic that I need for selecting a single clock among four possible clock sources. I'd like to select the source using a simple 4 way mechanical switch.
The sources are:
22....
- 511
0
votes
0
answers
59
views
How to choose between different equivalent PLL/divider configurations?
If there are multiple ways to get the required clocks for a given CODEC, how do you choose between them?
For example, if a CODEC can accept 64fs, 128fs, 256fs, and has an internal PLL that can ...
- 28.9k
1
vote
1
answer
429
views
I2S Clock in Audio Codec on dev board, how is this working?
I'm using a dev board, the keil mcb4300. In the schematic, the audio codec UDA1380HN has the BCKI going to the SYSCLOCK.
According to the codec data sheet:
BCKI: bit clock input
SYSCLOCK: system ...
- 397
1
vote
2
answers
3k
views
Generating i2s Clock Signals
I am trying to design a Pi Hat to integrate my Raspberry Pi 3 for use as an automotive head unit. I have a Texas Instruments TAS6424 and some supporting components, and am trying to design a DAC PCB ...
3
votes
3
answers
8k
views
How to decide about master or slave mode in I²S (I2S)?
Participants in I²S can be in master or slave mode. The master has to provide the clock and the slave has to accept the clock.
I would like to know how under what considerations this decision is made....
- 133
0
votes
2
answers
629
views
Interfacing Atmel Processor with i2s codec
I would like to interface an ATSAMS70 with a CS42L51 but this is my first time doing so.
The connection would be this:
MCLK - PCK2
SCLK - TK
LRCK - TF
SDIN - TD
SDOUT - RD
The thing is about the ...
- 163