I don't understand why the gate charge curve (exactly: the Miller plateau part) of MOSFETs is dependent on the drain-source voltage Vds.
As an example, the datasheet of of the IRFZ44 shows on page 4 (Fig. 6) the gate charge curves for different Vds values.
Why is the Miller plateau longer for bigger Vds? Isn't the plateau dependent upon Cgd? But Cgd (= Crss) gets smaller for bigger Vds (see FIg.5 in datasheet). Shouldn't the Miller plateau get shorter?
"Why is the Miller Plateau longer for bigger \$V_{\text{ds}}\$? "
The short answer is that Miller Plateau width scales with the area under the curve for \$C_{\text{gd}}\$. But why?
What does the Miller Plateau show?
The Miller effect exists because there is effective capacitance between the drain and gate of the FET (\$C_ {\text {gd}}\$), the so called Miller capacitance. The curve of Figure 6 in the datasheet is generated by switching the FET on with a constant current into the gate, while the drain has been pulled up through a current limiting circuit to some voltage \$V_ {\text {dd}}\$. After the gate voltage rises past the threshold and drain current reaches it limit (set by the current limiting circuit), \$V_ {\text {ds}}\$ starts to fall, displacing charge on \$C_ {\text {gd}}\$ through the gate. While \$V_ {\text {ds}}\$ falls to zero volts, from \$V_ {\text {dd}}\$, \$V_G\$ is stuck by the displacement current from \$C_ {\text {gd}}\$ ... that' s the Miller Plateau.
The Miller Plateau shows the amount of charge in \$C_ {\text {gd}}\$ by its width. For a given FET the width of the Miller Plateau is a function of the voltage traversed by \$V_ {\text {ds}}\$ as it switches on. The figure shows \$V_G\$ aligned with \$V_ {\text {ds}}\$ to make this clear.
The gate charge curve for the IRFZ44 shows three spans of \$V_{\text{ds}}\$; Span1 is 0V to 11V, Span2 is 0V to 28V, and Span3 is 0V to 44V. Now, some things should be clear:
Do these conclusions seem too hand wavy and snake oily to you? Ok, then how about this?
Why the Miller Plateau gets Wider for Higher \$V_{\text{ds}}\$ -- A Quantitative Look
Start with the equation for charge on a capacitor:
Q = CV with a differential form dQ = C dV
Now \$C_{\text{gd}}\$ is not a constant, but some function of \$V_{\text{ds}}\$. Looking at the curve in Figure 5 of the IRFZ44 data sheet for \$C_{\text{gd}}\$, we want some equation that is not infinity at zero \$V_{\text{ds}}\$ and falls off exponentially (ish). I won't go into any details here about how this was done. Just choose very simple forms that seem to match and try fitting them to the data. So, not based on device physics, but just matches pretty good with pretty little effort. Sometimes that's all that's required.
\$C_{\text{gd}}\$ = \$\frac{C_{\text{gdo}}}{k_c \text{V}_{\text{ds}}+1}\$
where
\$C_{\text{gdo}}\$ = 1056 pF
\$k_c\$ = 0.41 -- an arbitrary scaling coefficient
Checking this fitted model to the datasheet we see:
\begin{array}{ccc} V_{\text{ds}} & C_{\text{gd}}\text{(data)} & C_{\text{gd}}\text{(model)} \\ \text{1V} & 750pF & 749pF \\ \text{8V} & 250pF & 247pF \\ \text{25V} & 88pF & 94pF \end{array}
So, after plugging the \$C_{\text{gd}}\$ model expression into the differential form of the charge equation, and integrating both sides we get:
Q = \$\frac{C_{\text{gdo}} \log \left(k_c V_{\text{ds}}+1\right)}{k_c}\$ = \$\frac{\text{1056 pF } \log \left(\text{0.41 } V_{\text{ds}}+1\right)}{\text{0.41 }}\$
A plot of Q shows that it always increases for larger changes of \$V_{\text{ds}}\$.
The only way this would not be true would be if \$C_{\text{gd}}\$ became negative for some values of \$V_{\text{ds}}\$, which isn't physically realizable. So, more is more.
Once the MOSFET starts to conduct, there are carriers in the channel where there none before, and the gate-to-channel capacitance goes up, not down. Note that the capacitances measured in Figure 5 are all at VGS = 0.
Since the magnitude of the channel current for a given VGS is somewhat dependent on VDS, so is the increase in effective capacitance.
The position of the second "knee" in the curve represents the point at which the channel current stops increasing for a given VDS.
Greater drain voltage means more charge on Cgd. It is that simple. The current through Cgd determines the rate of change of voltage on Cgd. This current is Ig which is limited by the source so it takes more time to discharge more charge.
This video, explains the miller plateau similarly to gsills, but in animated form. Hope it helps :)
