I have a limited knowledge about BJTs used as amplifiers, but I know there is a voltage regime where the BJTs amplify, below saturation. I am wondering if I put an RC delay circuit on the BJT's base and have the emitter connected to ground. Will at some point I be amplifying? Should I use an FET to avoid this behavior? I intend to use both the PNP and NPN as switches.
The lower transistor in your circuit will be "amplifying", as you put it, when its base potential is between 0.5V and 0.6V (very approximately).
In other words, it will only be between "completely off" or "completely on" when the base is outside that range of potentials. As your input switches between 0V and 5V, the base will transition between 0V and 0.7V.
How long it spends between 0.5V and 0.6V depends on how quickly C1 charges, which will be related to the time constant C1×R1. The base's traversal of the region of "linear operation" could be a small fraction of the time it spends outside that region.
A FET will have different thresholds, but it will still be subject to a region of linearity, in which it's between fully off and fully on.
That said, your circuit will work, but requires a small change:
simulate this circuit – Schematic created using CircuitLab
R3 is required to limit current drawn through Q2's base via Q1.
Even though the lower transistor switches on rather sluggishly, the combined gain of both means that the upper transistor will make the transition mush faster, so fast that this circuit will probably work just fine.
The bigger issue is that the lower transistor will switch on very early in the capacitor's charging cycle, when the capacitor voltage has barely got off the ground. This, combined with the large variability in the transistor's "threshold" base potential, means that's it's difficult to get a precisely defined delay.
The threshold can be raised, to somewhere nearer the mid-point between the supplies (like +3V) by using a MOSFET. In fact by using two MOSFETs, you can get rid of R3 again:
The switching threshold will be close to Q1's \$V_{GS(TH)}\$. I would recommend \$V_{GS(TH)}\approx 3V\$. The upper MOSFET must also have \$V_{GS(TH)}\$ significantly smaller than the power supply, to be switched on properly when Q1 pulls its gate low.
There are only three practical solutions (that I can think of) to the problem of transition through the linear region, which are:
Make the transition as fast as possible
Make the linear region as small as possible
Positive feedback for hysteresis
The first two sound like hacks, but consider that the analogue domain is about all the voltages between two extremes, and the digital domain concerns itself with only the extremes; the difference between them is only interpretation, and they both rely on the same underlying physics.
To implement a digital system, we still have to rely on fundamentally analogue technology, but we try to get signals to transition between extremes really fast, so they spend as little time as possible in the "grey" area.
Even digital systems have to deal with and produce real-life analogue signals which traverse all possible values between some low potential (0V) and high (+5V), it's just that the traversal is really, really fast.
When interfacing signals from the analogue world, such as that produced by R1 and C1 (a slowly rising or falling potential) with a digital system expecting ,say, 0V and 5V (and spending very little time between the two), the archetypal device of choice is the comparator. The "jelly-bean" model is the LM393. Even analogue to digital converters make use of comparators in one form or another.
The comparator has two inputs. It compares their potentials, and produces a digital output that is high or low depending on which is greater. This is similar in behaviour to a bipolar or field effect transistor, except that:
Its linear region is absolutely minuscule. The time it takes for even the slowest changing input signal to traverse that region is next to nothing, and the transition through that region is, for all intents and purposes, zero. Consequently the output swings between minimum and maximum almost instantly.
You are responsible for both input potentials, which gives you complete and precise control over the switching threshold. Contrast that with FETs and BJTs, which define (very loosely) their own thresholds.
With all that in mind, here's how we'd use a comparator, the LM393, to perfom the function you require from your own circuit, but with much improved performance, flexibility and predictability:
I apply a square signal at IN, which results in a slowly rising and falling potential at the non-inverting input (X) of the comparator. The other input, inverting (Y), has a fixed potential half way between the supplies, +2.5V, provided by R2 and R3.
The comparator output Y is high when the potential at X is greater than Y, and vice versa. Here's a plot of all those potentials:
Notice how the output transitions (tan) between high and low follow the digital input (blue), delayed by a little under 1s.
The comparator output is used to switch on and off a MOSFET instead of BJT, for lower losses, and this switches on or off power to the load.
The advantages over a BJT/MOSFET implementation are several:
The switching threshold is very easily and precisely set by R2 and R3. The ambiguity and uncertainty of a BJT's or MOSFET's threshold is gone.
The switching threshold is higher than 0.7V, meaning that the switch occurs much later in the charging curve of the capacitor. This enables you to use a smaller timing capacitor.
The current drawn by the comparator input is negligible, in contrast to the current drawn by a BJT base. This enables you to use a larger timing resistor, and much smaller capacitor.
Input potentials are not constrained to a BJT's maximum of 0.7V. Together with the last point, this frees the capacitor to charge all the way to the supply potential, making its charge/discharge curve very close to ideal, and calculation of the exact moment at which the capacitor voltage crosses +2.5V is easy and precise.
The traversal of the linear region at the inputs is so quick, that the output spends no time in between the power supplies. Output transitions are emphatic, very "digital".
I should point out that technically, there's no "linear region" for most comparators (LM393 included). Internally they employ positive feedback to implement input hysteresis. As the input potentials pass other, the comparator adds/subtracts a tiny extra potential (1mV or so) to the non-inverting one, "moving the goalposts", so to speak. This positive feedback has the effect of reinforcing the new state, removing any ambiguity about which is greater, and effectively nullifying any linearity.
Having mentioned hysteresis, and how it completely eliminates any region of linear behaviour, I feel compelled to show you how we can apply this principle to the MOSFET circuit from before (it's more complicated for BJTs, but still possible):
The combination of R3, R4 and D2 allow the rising output (due to Q2 beginning to turn on) to further "pull up" the very signal that is causing it to rise in the first place, reinforcing Q2's transition to the on state.
One of the side effects of this positive feedback is a shift in the input threshold at which Q1 will switch off again, but when that lower threshold is reached, and Q2 begins to turn off again, the falling output lowers Q1's gate potential, reinforcing the condition that led to Q2 to initially start turning off.
The distance between the two thresholds is the hysteresis, and is shown as the two green markers.
Not only do we have no region of linear behaviour, but the transitions at OUT are accelerated and unambiguous.
Once again, though the comparator wins hands-down for simplicity, configurability, predictability and precision. I do exactly the same as before (except there's no diode) below. R5 and R6 apply a small amount of feedback to the non-inverting input, for positive feedback, with the attendant hysteresis and even sharper output transitions:
Consider this answer just an introduction to the excellent, but much longer answer here.
Perhaps simulating your circuit will help you understand the behaviour, and you can adjust values. Note in particular it has an added pulldown resistor R3 to get measurements to ground. And that, like original question, does not have a required current-limiting resistor on the base of Q2, which this kind of simulation will help you understand.
It has this response:
simulate this circuit – Schematic created using CircuitLab
This is somewhat aside the question directly asked, but useful information around it.
Note that, as the capacitor charges, base current starts to flow, slowing charge. As it charges still further, base current goes up exponentially, i.e. base input impedance drops exponentially, shunting more and more of the input current. Very quickly, the capacitor has almost no contribution anymore, and the circuit behaves pretty much as a normal switch.
This is easy to see in the hybrid-pi BJT model:
simulate this circuit – Schematic created using CircuitLab
where Rpi and Ic depend on Vbe. As Ic increases, Rpi decreases, lowering the Thevenin resistance at the base, thus lowering the RC time constant as the transistor turns on.
Sometimes, a slow turn-on (or off) is desired, even for switching purposes. In that case, reducing base current (by avoiding saturation) can be a viable strategy:
Here, a current limiting emitter resistor is used, making it a transconductance amplifier (current output, voltage input). The Q1 collector output has high impedance, making this excellent for level shifting purposes: Q2 gets the same base current for V2 anywhere from say 6V (or below, if a base-GND resistor is added at Q1, or a lower input voltage is used), up to 60V or so -- or more for higher voltage transistor types.
(Conversely, if speed is desired, omit C1, and add a small capacitor in parallel with R3 -- typically 100pF would be enough. This boosts collector current on the rising edge, turning on Q2 faster at no expense to steady-state losses.)
I also opted for 2N4403 for the PNP, to illustrate the current amplification available here; quite a strong load can be driven from just two transistors (100s mA), if R3 is decreased a bit (and maybe R1).
We can also avoid the base current effect by using a second base resistor:
This way, as Q1 turns on, the Thevenin impedance seen by C1 varies from a maximum of 100k, to a minimum slightly above 50k. The time constant is more predictable, giving more symmetrical rise and fall delays.
Notice this version saturates, so the current-limiting resistor R3 is necessary, and Q2 base current depends on V2 so it's less flexible than the previous case.
Digital applications for slow switching include low-bandwidth, EMI sensitive applications like status signals on field wiring (say for automation, commercial and industrial installations), where sharp edges would otherwise cause radio interference on such long wires (antennas). And remember, slow is relative: communications channels of quite practical bandwidth (100s kbps?) can benefit from this; take for example RS-232, an intentionally slowed (slew rate limited) single-ended signaling standard.
It can also be useful for load switches, where the soft start reduces inrush current into a capacitive load, or reduces peak overvoltage on an inductive load.
