TL;DR: The ADC is on an analog ground plane that is connected to the digital ground plane by a single segment 10 mil trace, about 1.3" away from the ADC, away from digital signals straddling the plane split. And then the ADC has a DGND trace going to the digital plane. And the analog circuitry has no power plane. It's all traces and capacitors...
And then the digital side... has no power planes, just ground planes. The power goes around on 25 mil traces...
And the ground planes are not stitched, other than a half-hearted effort done at the AGND plane border...
Yeah, no. Even if this somehow, magically, will begin to "work", it'll be failing in the field. This is an EMC nightmare, a susceptibility nightmare... Just no. It's a tour-de-force in what not to do. Amazing.
It is unlikely that the manufacturing has anything to do with the problems. Unless fake parts were used, it almost never is the problem in such designs - not with the symptoms you observe, not when the design has never worked before, and not when you don't have a bunch of working designs behind you already. And even if you got bad boards and fake parts, the layout itself makes it a no-go.
As seen on the sample of the layout you posted: the AGND/DGND split is likely the root of all the trouble. When you do a design, start with one ground plane, solid and uninterrupted, with only vias making holes in it. Split the planes only if/when needed. Prefer to keep unwanted signals local by routing and minimizing loop areas rather than plane splitting. It's OK to have local impedance-reducing planes under switching regulators and such, but in most cases ADCs work just fine with one analog+digital plane as long as the ADC's package design is sensible, and as long as the board cleanly separates the analog and digital circuitry on opposite sides of the ADC.
This board has so much empty room that there's no need for split planes. Just the physical separation will ensure that digital return paths won't pollute analog signals - assuming the routing of those is done appropriately.
DGND is the return path for all of the digital signals going to/from the ADC. But you run them over the AGND plane, and DGND is just a trace... This has approximately zero chance of working properly - the digital signals are corrupted badly, if you only measured them. You're extremely lucky that this problem has shown up now, rather than later. It wouldn't take much - just a slightly different routing for some traces - for the design to appear to "work" - except the eye patterns on all the digital signals would be despair-inducing, and the design would be an EMC nightmare. This thing must radiate quite well, and - conversely - it's also susceptible to digital noise nearby.
I've reviewed the Gerbers... it's worse than I thought. I'm amazed this works at any temperature...
The ground plane splits must go. All of them. Start with a single solid ground plane. And before you add any splits, have it manufactured and working at least once with a solid plane. Then understand exactly the return current paths for all the signals that will cross the split. And then remember that nothing digital that doesn't have carefully controlled edge slew rates can cross any splits whatsoever.
Ask someone with experience in signal integrity to explain this, since it'll be much faster hands-on than over the internet. Writing up the do's and dont's of this design would take me a solid day of work. I'm amazed that such a project at such a respectable institution would be essentially free-running without guidance from people who have some industry experience doing such layouts. This should have never made it to production as-is.
Ground plane splits are for the experts. Do not attempt if you're a novice without solid grounding in signal integrity - splits will always make your life a million times harder.
Do not blindly follow datasheet advice in this matter: a lot of the "advice" requires solid understanding of where it comes from. The advice is often more a reminder to professionals about what they should not forget or at least consider, rather than something to just take on faith.
Since you're at Drofnats, I imagine someone at EE will have an EM modelling setup that can extract the lumped model for any of the signal traces on the board, based on the gerber layout and board stackup. I highly suggest you get this for a couple of digital signals going between ADC and MCU, stick it into spice - even CircuitLab on this site will be enough - then dump some suitably fast pulses into this transmission line model and see what happens. It'll be wondrously amusing and educational, and it's basically a must see if you haven't gotten a TDR and some bare boards to play with (and someone to explain how to "ping" signal traces accurately using a TDR).
If you want more help with this, make sure there are PDFs of the schematics in the repo. Not everyone uses Altium.
