Routing traces over traces in two layer pcb

Question

I am kind of new to PCB Design. I have a few confusions on my board layout, in order to reduce EMI in routing. I am designing a two-layer PCB design

1. I am aware that when you route traces over different layer and if they cross each other, coupling occurs between the cross-sectional area where the two traces meet as they create a parasitic capacitance. But if it definitely has to cross, then it has to cross at 90 degrees. My question is: Is this applicable for all kind of traces where a power trace crosses an analog or digital trace?

2. Since the power trace has the lowest impedance because of its wider trace, is it possible to crossover two power traces on different layers?

3. How wide should be the trace length, if I am taking it all over the board for a star connection (as daisy chaining is a bad practice)?

4. Is it correct to add decoupling capacitors on the cross-sectional area over the weaker trace?

I am working with low power circuits, where the voltage is 3.3V and the microcontroller runs at 8 MHz, a 1 MHz buck-boost with a couple of analog and digital sensors. I have also made sure that the analog and digital ground are separated and directly meet at the origin (i.e. a battery).

Also, is there any signal integrity simulation software available as open source?

Any suggestions and tips apart from this are also welcome. Thank you.

Answer 1

The points that you have highlighted are all valid, but don't really apply to your design, as a 8MHz microcontroller is not really considered high speed. In terms of EMI, what you should look at is rise time, rather than clock frequency, as the 8MHz frequency itself doesn't really cause issues, but a 1Hz signal with a fast rise time, can cause havoc.

To answer your questions:

1. It is good practice to avoid crossing other signals, but the reason for having a 2 layer board is mostly because you need signals to cross. In general terms, you should only avoid crossing signals that can interact with each other, for example keep well away from each other an SPI clock from an ADC input, if these are likely to be working at the same time, but if these are active at different times, then the issue doesn't exist. In essence, be pragmatic.
2. Power traces can cross over each other without any issue, as long as they are not noisy. For example, a power line that drives a motor should not cross over the reference voltage of an opamp. Again, be pragmatic.
3. Daisy chaining is not a problem, as long as you keep into consideration what is powered by this line. The width is proportional to the length and the amount of current that goes through this trace. As a rule of thumb, go as wide as you can, but don't forget that the return path should be at least just as wide.
4. Only on hi-speed designs. Don't worry about that on your design.

As you can see, there is no golden rule, PCB design is mostly about compromises. You could follow all of the best practices for signal integrity, and you would end up with a very expensive multilayer board that is space-grade, but you need to ask yourself the question: "is that what I need?"

The first step in the design is to look at the recommended layout in the datasheet. If you follow that, you should be ok in 99% of cases, especially in the buck/boost converter. The design you are working on sounds very much like it is very similar to an Arduino board. you can download the design files one any of them, and have a look at the layout. That will give you a

Answer 2

2)To reduce EMI it is nice to have one layer where you have the signals, and one where you have only ground. Of course that's not always possible for signals, but for power traces it is very strongly recommended. If you have a 2 layer design and two power layers overlap, it means that you just build a big antenna which can cause all sorts of EMI problems, not to mention that your power signal will not be clean.

3) The width of power traces depends on how much current is supposed to flow through them, but also on how thick the copper layer is (35um, 70 etc...); in the end you will have a temperature increase which should be acceptable. There are many helps out (trace width calculators).

4) Decoupling capacitors should be placed as near as possible to the relevant ICs. Generally speaking signal traces can be routed under resistors or capacitors without problems. If you can avoid it, don't place sensitive signals under ICs (and never under switch mode dc/dc converters!).