I've got the following layout for 4 layers PCB, I would like to know why there are so many vias on the ground trace.
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2\$\begingroup\$ This board causes more questions than you asked. Is top layer filled with ground polygon? What is to the right - connector? Why 4-layer? What is at the bottom? Please ask developer of the board what he or she thinks about it all. \$\endgroup\$– AnonymousCommented Nov 1, 2018 at 7:56
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4\$\begingroup\$ @Anonymous right looks like the side of a QFP to me \$\endgroup\$– Jasen Слава УкраїніCommented Nov 1, 2018 at 8:03
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\$\begingroup\$ No, it is not filled with ground polygon. The chip to the right is stm32 microcontroller. 4-layer because the space is very restricted. The chips at bottom are bypass capacitors for the microcontroller. \$\endgroup\$– ShadiCommented Nov 1, 2018 at 8:04
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\$\begingroup\$ @Jasen yes it is. \$\endgroup\$– ShadiCommented Nov 1, 2018 at 8:08
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\$\begingroup\$ @Jasen thanks, now I see it. Should have guessed by the silkscreen and partial dot at the top! \$\endgroup\$– AnonymousCommented Nov 1, 2018 at 8:11
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2 Answers
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We are clear now that it is microcontroller with two crystal-based clock circuits attached to it. My guess is that signal layer below the top one is ground, and these vias connect the red tracks around the crystals to that layer, I guess "to make better ground". But that may not be the best solution in such circuits.
As I said in the comment to the questions the best is to ask developer of the board the following questions:
- Why did not he consider putting bigger ground polygons at th top layer as it is clear that there're no components around the crystal circuitry?
- Did he simulate the circuit and perform impedance/EMI check as the generating components are relatively close to each other?
- Did he consider the negative effects by putting vias creating ground loops?
And finally, there must be a clock generation circuit layout guideline in the datasheet or application note of the STM32 microcontroller, which should be followed as much as possible given design contraints.
Update: I asked my friend who specializes on the stuff, and his feedback was that actual layout would depend on the frequency, and that ground polygon (instead of separate tracks at the top) would do better job in shielding.
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\$\begingroup\$ @ Anonymous thank you very much. Exactly, the second layer is ground. But that may not be the best solution in such circuits (do you mean by putting bigger ground polygons? ). Your questions are helpful. Thanks \$\endgroup\$– ShadiCommented Nov 1, 2018 at 8:32
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They are stitching vias, to keep the high frequency crystal lines from interfering with the rest of the circuit. Imagine the vias are like the side walls of a faraday cage, and the traces are the roof and floor.
Altium have an article on why and how to add them: https://www.altium.com/documentation/15.1/display/ADES/((Via+Stitching+and+Via+Shielding))_AD
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\$\begingroup\$ @ MIL-SPEC Thank you. So, it means that those vias act like antennas that take all high frequency signals away from the rest of the circuit! \$\endgroup\$– ShadiCommented Nov 1, 2018 at 8:55
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1\$\begingroup\$ @ Shadi Another way to think about the pieces of metal, given this is a very small regions, is their value in capturing Electric Field flux (think of capacitive coupling, using the parallel-plate capacitive math C = EoErArea/Distance). This small region will be NEAR FIELD, and electric-coupling is a fine way to model the interference. So, yes, like a Faraday Cage. Unless you also have some fast dI/dT currents, in which case some magnetic coupling may be problems. \$\endgroup\$ Commented Nov 1, 2018 at 14:28