KiCad Bus on multiple sheets - Are labels the right way to go?

Question

I want to connect bus-lines via several-sheets in KiCAD 5.0 But I don't know whether I got that right. Please consider the following design:

Shown in Figure 1 you can see my connection from the chips output to the signal-bus. I added hierarchical labels to each bus. Those were added with the following function:

Figure 2 shows the parent-sheet in which the network-logic- and the plug-sheet live. There I then added the hierarchical pin with the following function:

I added the label and the bus on the plug side the same way, as shown in picture below.

Question:

1. Is my bus now connected correctly, or am I using the idea of labels wrong?
2. Do labels work with busses the same way the do with single wires?
3. Is it correct, that every line from a bus that has the same name, will be connected in the net-list?

Answer 1

1. Is my bus now connected correctly, or am I using the idea of labels wrong?

Local labels (in your example, these are LED1, LED2) will all be connected. So in your first image, the pin for LED1_0 and LED2_0 will be connected. This is probably not what you want. You should prefix each wire in a bus with the same string. So ETH1_LED1 and ETH1_LED2 for bus ETH1 and ETH2_LED1 and ETH2_LED2 for bus ETH2.

2. Do labels work with busses the same way the do with single wires?

No. There are some bus-specific label requirements (see https://docs.kicad.org/5.1/en/eeschema/eeschema.html#connections-buses)

3. Is it correct, that every line from a bus that has the same name, will be connected in the net-list?

Wires connected to buses need to have a local label attached to them identifying which bus member they are connecting. Each bus member needs to have the same alpha-numeric prefix (e.g. ETH1_LED) and a numeric suffix.

Answer 2

Beginning with KiCad 6.0 it's possible to solve this in a multisheet friendly way.

Busses may have names and those names may be aliased to each other. To access a net in one bus it's done by writing BUSNAME.NETNAME. To satissfy the ERC check however the hierarchy pin needs to be defined as a bus containing the correct nets, eg SPI{CLOCK MISO MOSI}. Thankfully this can be shortened by Bus Definitions for large busses found under Tools to SPI{SPI_def}.

One Example:

P1: P2:

All pictures were taken with the same net selected. The resistors are there to show which peripheral is currently open.