Beitrag von HEITEC AG

🏆 Congratulations to Wanghua Wu and her fellow team members at Samsung Semiconductor & Samsung Electronics for achieving the 1st Place Industry Awards! The authors delve into the design and architecture of a 14nm FinFET IF-IC tailored for dual-band 5G-FR2 transceivers with an aggregated bandwidth of up to 1.4GHz. Their research highlights an impressive cascaded dual-PLL rms jitter of 114fs, enabling robust support for up to 256-QAM, all while maintaining competitive power consumption levels. Abstract "We present a low-cost dual-stream IF transceiver IC (IFIC) for 5G mm-wave mobile applications. It up/down-converts the baseband signal to an intermediate frequency (IF) of 8.4–10 GHz and forms a heterodyne transceiver system together with beamforming ICs to support all FR2 bands from 24.25 GHz to 43.5 GHz. The IFIC features a compact transceiver RF circuitry, low-jitter reconfigurable LO suitable for 256-QAM and non-contiguous carrier aggregation, and an integrated MCU in the digital baseband for flexible calibration and control of both transceiver ICs. The IFIC is implemented in 14-nm FinFET and occupies 16.2 mm2. The overall chain IPN measured at 39-GHz band is as low as 114 fs. Thanks to the flexible calibration architecture, digital-pre-distortion (DPD) is demonstrated in TX, which allows for >1 dB of increase in EIRP for both DFT-s- and CP-OFDM signals at EVM of 5.5% at 39-GHz band." More details on the IEEE Xplore: https://lnkd.in/gKqyfJDf 📌 Consider submitting a paper to the IEEE RFIC Symposium! #rfic2023 #rfic2024

Advanced #embeddeed Solutions including #Video, #Graphics and fast & intuitive #HMI or demanding #algorithms mostly need #MPU with operating systems like #Linux in the background. Please learn in this seminar on the advantages and disadvantages in either making it yourself or in buying a embedded solution. You can decide on "#Make or #Buy" not only for the whole package, but also separately for #Hardware, #Software or just building blogs like a Board Support Packages (#BSP). The "Make or Buy" decision often is a question of the strategic #focus of a company and where its key know-how lies. Please register now for this seminar in #Berlin area. This seminar is presented by - Ester Vicario Bravo (NXP Semiconductors) - Gerard Ram (EBV Elektronik) - Guido Jäger (Avnet Embedded) - Cirus Coliai (Witekio)

Still in anticipation and preparation for the PICO Chipathon , the workhorse of integrated circuits , amplifier, seem to be the topic for today again. Below is a document on its different topologies and configurations there can exist at the simplest stage and the common characteristics as well. #100daysofamplifierdesign #PICO #IEEE Pipeloluwa Olayiwola TSMC IEEE Solid-State Circuits Society Intel Corporation Samsung Semiconductor Texas Instruments

A very interesting #article from Radomir Novotny about the return of #analogcomputers. Also the part about the practical applications of analog computers at the ZHAW School of Engineering (in Switzerland) is very interesting. So definitely an article worth reading! And https://lnkd.in/eyJFpbaF

That’s a wrap! The 2023 IEEE VLSI Symposium was a great experience, with lots of interesting discussions and works from both academia and industry. Backside PDN took the spotlight, and I am grateful for having the opportunity to contribute with a workshop and a paper! #imec pioneered this technology years ago, confirming its place at the forefront of innovation in the semiconductor industry. However, now we have a question to answer: “What’s Next After Backside Power Delivery?”

CFETs : Intel, Samsung, TSMC Showcase Future of Transistor Technology The semiconductor industry is witnessing a paradigm shift with the recent advancements in transistor technology. In a groundbreaking showcase at the IEEE International Electron Devices Meeting, three semiconductor giants – Intel, Samsung, and TSMC – presented their progress in developing complementary field-effect transistors (CFETs). This blog post aims to provide an in-depth comparison of the CFET developments from these three industry leaders, exploring the unique features, innovations, and potential implications for the future of semiconductor technology.

The evolution of #FPGA architectures has brought us to a turning point in the way we think about system design. With the dramatic increase in logic density and heterogeneous integration of compute engines, the associated tool flows, IP, and software stacks need to evolve as fast as the silicon. 🎤 In this session by keynote speaker Michael Hutchison from AMD, you'll learn about the transition from FPGAs to adaptive SoCs, from programmable logic to Arm® subsystems and vector processors, and how AMD is spearheading this transformation with Versal™ adaptive SoCs and next-generation AI Engines. Take your chance and register today for FPGA Conference Europe with an early bird discount: 👉https://lnkd.in/eZHeFdPF PLC2 #FPGAConference #embeddedsystems #adaptivecomputing

Embedded World '24: Demos based on the Lattice CrosslinkU-NX33 FPGA with a USB3 core. Lattice Semiconductor invited tinyVision.ai to present their demos based on the CrosslinkU-NX FPGA family. We presented the following 3 compelling demos at the conference. 1. High bandwidth demo: The FPGA can be used as a fat pipe for applications such as Software Defined Radios, test equipment such as logic analyzers. A 2 Gbps application layer throughput was achieved at this early stage of the project. We expect to see about 3.4Gbps once everything is optimized. 2. UVC: An often requested use case is the ability to connect multiple cameras, do some basic ISP and ship this out as a USB stream. This demo was done in collaboration with the talented team at https://emcraft.com/. The FPGA enumerates as a UVC device and streams video. 3. QR code detection and decoding: Using a simple neural network, we demonstrate QR code detection on the FPGA. This demo was in collaboration with our partner, https://streamlogic.io/, a drag-drop tool designed to accelerate RTL development. For more details, please visit: https://lnkd.in/gtZw_DEi #latticesemiconductor, #ewc, #fpga, #usb, #embedded, #computervision

Join us for an insightful presentation about Digital Radar by Bernhard Wandl at the FPGA Conference, who has been exploring this topic in cooperation with Hagenberg Campus - FH Upper Austria, Silicon Austria Labs (SAL), JKU and Infineon Technologies. 🔍 Bernhard will discuss the advanced features and applications of the AMD UltraScale+™ RFSoC FPGA series, highlighting a digital radar implementation. This series, with its high-end RF measurement capabilities and powerful FPGA fabric, is well-suited for digital radar applications. It includes 12-bit ADCs with a maximum sampling rate of 4 GSPS and 14-bit DACs with a maximum sampling rate of 6.5 GSPS. These high sampling rates, combined with the tight integration of the FPGA fabric, enable the transition of many signal processing tasks from the analog to the digital domain, utilizing direct digital synthesis for TX signal generation. 🚀 #P2L2 #FPGA #FPGAconference #Innovation #DigitalRadar #RFSoC #FHhagenberg

The recent International Memory Workshop in Seoul between May 12 – 15 (https://lnkd.in/gRi-yVPf) had an excellent and thought-provoking keynote address from Kioxia’s 3D NAND expert, Ryota Katsumata (R. Katsumata, "Flash memory revolution: journey from 2D to 3D, migrating to modular memory fabrication," 2024 IEEE International Memory Workshop (IMW), Seoul, Korea, Republic of, 2024). Coverage and interesting discussions of this have been dealt with by PC Watch and Blocks & Files at https://lnkd.in/gGzh8Eyq and https://lnkd.in/g2saBKgX. Katsumata-san also kindly referenced one of my papers but more on that in another post (A. J. Walker, "A Rigorous 3-D NAND Flash Cost Analysis," in IEEE Transactions on Semiconductor Manufacturing, vol. 26, no. 4, pp. 619-625, Nov. 2013). The mantra is 100 Gbits/mm2 with 1000 layers by 2027. This emphasizes the prime importance of 3D NAND string length (in terms of the number of cells) in determining the memory density which contrasts with 2D NAND where string length was of secondary importance. The fact that each 3D NAND cell is made of a field effect transistor with a noncrystalline channel (and therefore high resistance) results in string current being a major challenge in achieving that 100 Gbits/mm2. No wonder there is significant research into removing the channel disorder such as MILC techniques which originally came from the flat panel industry. The physics of conduction in disordered semiconductors has therefore become a major focus of study. It turns out this has a longer history going back to before even 2D NAND was invented. Foundational work on amorphous silicon was done at the University of Dundee in Scotland in the 1970s by P.G. Lecomber and W. Spear. Various models were also developed for polycrystalline conduction at various institutes resulting in two main approaches: grain boundary energy barrier mediated conduction and an effective medium approach similar to amorphous silicon. Twenty years ago, we carried out an extensive experimental study of this conduction mechanism precisely for 3D Flash memory applications that resulted in a publication in the IEEE Transactions on Electron Devices. High level: an effective medium approach was able to describe all the behavior we saw over three different grain structured polysilicon channels. Predictions from the grain boundary barrier approach were experimentally absent. A summary is given below. It was a joyous exercise with great colleagues. #NANDFlash #3DNAND #3DNANDFlash #NAND #Nonvolatile #Memory #Storage