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    It's best to think of the address space as a big space in which things can be assigned by hardware. When the CPU reads/writes memory, it actually performs a communication over a bus, and hardware can make sure things like RAM or ROM is responding at specific address ranges. So such hardware would have to make sure a ROM responds at 0xFFFFFFF0 when the CPU is reset. There is no inherent obligation that ROM appears right after RAM. It can appear wherever the hardware tells it too, depending on the capabilities of such hardware.
    – LawrenceC
    Commented Oct 19, 2015 at 2:21
  • 4
    It's possible to have "holes" or unassigned spaces that aren't used by ROM, RAM, or anything - typically accessing those will cause a system lockup.
    – LawrenceC
    Commented Oct 19, 2015 at 2:22
  • 19
    This answer assumes that the CPU can use 32 address bits while in 16 bit mode. But in 16 bit mode it can only use 20 address bits. The address 0xFFFFFFF0 is not reachable until after the CPU has been switched to 32 bit mode. Last time I looked closely at BIOS code, the entry point was at 0xFFFF0.
    – kasperd
    Commented Oct 19, 2015 at 7:27
  • 6
    @MichaelKjörling your calculation is wrong. Shifted segment and offset are not ORed, they are added. Thus logical FFFF:FFF0 is physical (1)0FFE0 (where leading 1 is present if A20 is enabled).
    – Ruslan
    Commented Oct 19, 2015 at 9:58
  • 10
    @kasperd There's a hack in place - the memory manager has the high 12 bits set to 1 until the first long jump takes place. So yes, logically, you're working with 0xFFFF0, but in reality, it maps to 0xFFFFFFF0. I expect this was done for compatibility with the 8086 - both it and more modern CPUs appear to use 0xFFFF0, but the 32-bit CPUs actually access 0xFFFFFFF0 (mapped to BIOS ROM).
    – Luaan
    Commented Oct 19, 2015 at 13:24