The xhci specification clearly states that an individual controller may support multiple "bus instances", each representing a bandwidth unit, e.g. 480 mbit for high-speed. See the second and third paragraphs in section 4.6.15. The example provided there is 1 SS + 2 HS + 4 LS/FS for 7 distinct BIs of bandwidth divvied up between 8 physical ports. I'd love to know whether any shipping hardware implementations go the extra mile to implement it. I haven't been able to find explicit mention in the documentation for various chipsets. Given that superspeed-to-highspeed transaction translators are conspicuously absent from the USB3 spec, it would seem the best way to support a large complement of bandwidth-hungry USB2 devices.

The xhci specification clearly states that an individual controller may support multiple "bus instances", each representing a bandwidth unit, e.g. 480 mbit for high-speed. See the second and third paragraphs in section 4.6.15. The example provided there is 1 SS + 2 HS + 4 LS/FS for 7 distinct BIs of bandwidth divvied up between 8 physical ports. I'd love to know whether any shipping hardware implementations go the extra mile to implement it. I haven't been able to find explicit mention in the documentation for various chipsets. Given that superspeed-to-highspeed transaction translators are conspicuously absent from the USB3 spec, it would seem the best way to support a large complement of bandwidth-hungry USB2 devices.