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I'd guess that CPU caches make shadowing even less relevant for BIOS code that has to run during bootup. If the memory regions containing the BIOS are marked cacheable (e.g. in the MTRR in an early stage of booting), loops and frequently-called functions don't need to re-fetch instructions off-chip each time. Unless there's some obstacle to caching for addresses that have to go to the system agent (not DRAM), like there is for MMIO regions. (Mapping MMIO region write-back does not work)
– Peter Cordes
Commented Aug 12, 2022 at 21:40
Anyway, if caching does work, Intel CPUs since Nehalem (with inclusive L3 cache) might sometimes evict a line from L1i cache / uop-cache if touching a lot of data evicts the line from the unified L3, e.g. during a memory test, but that'd be rare. I'd expect that usually an L3 cache of a few MiB would cover most of the data+code footprint of everything firmware does, maybe even including modern UEFI firmware menus with mouse support. (Although I could also imagine that code+data for fancy menus might get decompressed into RAM so it could take less space in flash memory.)
– Peter Cordes
Commented Aug 12, 2022 at 21:44

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