Timeline for Motherboard says PCIe 3.0, but chipset only supports PCIe 2.0. Who's right?
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| Feb 26, 2019 at 8:20 | audit | First posts | |||
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| Feb 20, 2019 at 18:26 | audit | First posts | |||
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| Feb 14, 2019 at 1:08 | audit | First posts | |||
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| Feb 8, 2019 at 19:31 | comment | added | Stephen Kitt | The X10DRi manual includes a block diagram on page 1-10 which shows how the lanes are split. Slot 2 gets 16 lanes to CPU 1, slots 1 and 3 get 8 lanes each to CPU 1, slots 4 and 6 get 16 lanes each to CPU 2, slot 5 gets 8 lanes to CPU 2. The PCIe 2.0 lanes from the chipset are used for the BMC. The X540/i350 LAN chipsets and the C612 are connected to CPU 1. | |
| Feb 7, 2019 at 22:19 | comment | added | Mokubai♦ | @WilliamHandrigan I found the Intel technical page that shows the effective layout. | |
| Feb 7, 2019 at 22:19 | history | edited | Mokubai♦ | CC BY-SA 4.0 |
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| Feb 7, 2019 at 22:05 | vote | accept | William Handrigan | ||
| Feb 7, 2019 at 22:01 | history | edited | Mokubai♦ | CC BY-SA 4.0 |
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| Feb 7, 2019 at 22:01 | comment | added | William Handrigan | Perfect. Thanks for your concise, timely response! | |
| Feb 7, 2019 at 21:58 | comment | added | Mokubai♦ | I've added details. The motherboard holds the PCIe connections from CPU to GPU, but they do not need to pass through the chipset. They are direct from the CPU to the CPU served PCIe slots. Somewhere in your motherboard documentation it should tell you if any of the PCIe slots are served by chipset or CPU. Chances are the chipset PCIe lanes are used to serve an m.2 slot or SATA controller. | |
| Feb 7, 2019 at 21:56 | history | edited | Mokubai♦ | CC BY-SA 4.0 |
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| Feb 7, 2019 at 21:56 | comment | added | William Handrigan | I understand the CPU can support more lanes, but does not the chipset actually define those lanes? In other words, do the lanes go from the CPUs, through the chipset, and then on to the GPU? | |
| Feb 7, 2019 at 21:54 | history | answered | Mokubai♦ | CC BY-SA 4.0 |