Timeline for RAM tests inconsistently - what is the most likely culprit? (i.e. what should I spend money on replacing)
Current License: CC BY-SA 3.0
11 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 22, 2016 at 8:44 | audit | First posts | |||
| Apr 22, 2016 at 8:45 | |||||
| Mar 28, 2016 at 21:08 | audit | First posts | |||
| Mar 28, 2016 at 22:45 | |||||
| Mar 28, 2016 at 14:46 | audit | First posts | |||
| Mar 28, 2016 at 17:42 | |||||
| Mar 28, 2016 at 0:59 | comment | added | alex.forencich | Definitely seems like a motherboard signal integrity issue. The larger modules could have higher capacitance per pin than the smaller modules, especially if the modules themselves are dual rank. This could cause exactly this issue when you fully populate the ranks. It is possible for a module to have more than one rank. So four ranks per channel could easily be two dual-rank high density modules. This could be exacerbated by the electrical characteristics and routing of the traces on the motherboard. My suggestion: try another motherboard. | |
| Mar 27, 2016 at 20:06 | comment | added | Ben Voigt | @brhans: It's not the timing parameters that matter, but the memory clock frequency, because the problem is in the transfer between the CPU and DIMMs, not internal to the DRAM. SPD usually has a number of profiles corresponding to different clock frequencies, choosing a different one of these would be better than going fully manual. | |
| Mar 27, 2016 at 19:56 | comment | added | Ben Voigt | @bwDraco: Even though the memory controller is on the CPU, the motherboard also matters. The PCB layout can affect it, suboptimal length matching will decrease the phase margin on the signals (this is also why errors correlate to certain bytes or bit positions). That the motherboard manual doesn't talk about ranks doesn't mean that all combinations are supported, it just means it's a crap manual that doesn't go into detail. | |
| Mar 27, 2016 at 17:54 | comment | added | bwDraco | I'm not sure whether this is actually correct. Consumer Haswell processors generally support four memory ranks per channel, which is enough to allow four double-sided modules in two memory channels. Why would this be the issue? This also doesn't seem to explain the fact that the problems only happen above the 4 GB barrier. Furthermore, the motherboard's manual states that the underlying B85 chipset supports 32 GB of memory and does not mention any limitation regarding the number of memory ranks. | |
| Mar 27, 2016 at 13:46 | comment | added | brhans | Assuming this is the cause of the problem, would it help to turn off SPD and tweak the timing settings a little slower to compensate for the slower rise/fall times? | |
| Mar 27, 2016 at 4:26 | history | edited | Ben Voigt | CC BY-SA 3.0 |
added 79 characters in body
|
| Mar 27, 2016 at 3:27 | history | edited | Ben Voigt | CC BY-SA 3.0 |
added 257 characters in body
|
| Mar 27, 2016 at 3:14 | history | answered | Ben Voigt | CC BY-SA 3.0 |